L8Hx('H@(,haoyu,marsboard-rk3066rockchip,rk3066a7MarsBoard RK3066chosenaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000/serial@20064000/serial@20068000/spi@20070000/spi@20074000memorymemory`@amba ,arm,amba-busdma-controller@20018000,arm,pl330arm,primecell @ apb_pclk00dma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk disableddma-controller@20078000,arm,pl330arm,primecell @ apb_pclk%%oscillator ,fixed-clockn6xin24ml2-cache-controller@10138000,arm,pl310-cache!/..scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer   local-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gic;Pserial@10124000,snps,dw-apb-uart@ "akbaudclkapb_pclk@Lokayxdefaultserial@10126000,snps,dw-apb-uart` #akbaudclkapb_pclkAMokayxdefaultusb@10180000,rockchip,rk3066-usbsnps,dwc2 otgotg@@  usb2-phyokayusb@101c0000 ,snps,dwc2 otghost usb2-phyokayethernet@10204000,rockchip,rk3066-emac @< D hclkmacrefdrmiiokay xdefault  ethernet-phy@0 dwmmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciuokayxdefaultdwmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciu disabledxdefaultdwmmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciu disabledpmu@20004000,rockchip,rk3066-pmusyscon @grf@20008000,syscon i2c@2002d000,rockchip,rk3066-i2c  (i2cP disabledxdefaulti2c@2002f000,rockchip,rk3066-i2c  )Qi2cokayxdefaulttps@2d-'3?KWco{ ,ti,tps65910regulatorsregulator@0vcc_rtcvrtcregulator@1vcc_iovioregulator@2vdd_arm '`vdd1regulator@3vcc_ddr '`vdd2regulator@5 vcc18_cifvdig1regulator@6vdd_11vdig2regulator@7vcc_25vpllregulator@8vcc_18vdacregulator@9 vcc25_hdmi vaux1regulator@10vcca_33 vaux2regulator@11 vcc_rmii vaux33  regulator@12 vcc28_cif vmmcregulator@4vdd3regulator@13 vbbpwm@20030000,rockchip,rk2928-pwm F disabledxdefaultpwm@20030010,rockchip,rk2928-pwm F disabledxdefaultwatchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3okaypwm@20050020,rockchip,rk2928-pwm  G disabledxdefaultpwm@20050030,rockchip,rk2928-pwm 0G disabledxdefaulti2c@20056000,rockchip,rk3066-i2c ` *Ri2c disabledxdefault i2c@2005a000,rockchip,rk3066-i2c  +Si2c disabledxdefault!i2c@2005e000,rockchip,rk3066-i2c  4Ti2c disabledxdefault"serial@20064000,snps,dw-apb-uart @ $akbaudclkapb_pclkBNokayxdefault#serial@20068000,snps,dw-apb-uart  %akbaudclkapb_pclkCOokayxdefault$saradc@2006c000,rockchip,saradc   GJsaradcapb_pclk disabledspi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk & % % $txrx disabledxdefault&'()spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @% % $txrx disabledxdefault*+,-cpus.rockchip,rk3066-smpcpu@0cpu,arm,cortex-a9<.(Mag8 s 'B@^@cpu@1cpu,arm,cortex-a9<.sram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPi2s@10118000,rockchip,rk3066-i2s  xdefault/00$txrxi2s_hclki2s_clkKl disabledi2s@1011a000,rockchip,rk3066-i2s  xdefault100$txrxi2s_hclki2s_clkLl disabledi2s@1011c000,rockchip,rk3066-i2s  xdefault20 0 $txrxi2s_hclki2s_clkMl disabledclock-controller@20000000,rockchip,rk3066a-cru timer@2000e000,snps,dw-apb-timer-osc  .VD timerpclkefuse@20010000,rockchip,rockchip-efuse @[ pclk_efusecpu_leakagetimer@20038000,snps,dw-apb-timer-osc  ,TB timerpclktimer@2003a000,snps,dw-apb-timer-osc  -UC timerpclkphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phyokayusb-phy0|Qphyclkusb-phy1Rphyclkpinctrl,rockchip,rk3066a-pinctrlgpio0@20034000,rockchip,gpio-bank @ 6U;Pgpio1@2003c000,rockchip,gpio-bank  7V;P  gpio2@2003e000,rockchip,gpio-bank  8W;Pgpio3@20080000,rockchip,gpio-bank  9X;P55gpio4@20084000,rockchip,gpio-bank @ :Y;Pgpio6@2000a000,rockchip,gpio-bank  <Z;Ppcfg_pull_default44pcfg_pull_none33emacemac-xfer33333333  emac-mdio 33  emmcemmc-clk4emmc-cmd 4emmc-rst 4i2c0i2c0-xfer 33i2c1i2c1-xfer 33i2c2i2c2-xfer 33  i2c3i2c3-xfer 33!!i2c4i2c4-xfer 33""pwm0pwm0-out3pwm1pwm1-out3pwm2pwm2-out3pwm3pwm3-out3spi0spi0-clk4&&spi0-cs04))spi0-tx4''spi0-rx4((spi0-cs14spi1spi1-clk4**spi1-cs04--spi1-rx4,,spi1-tx4++spi1-cs14uart0uart0-xfer 44uart0-cts4uart0-rts4uart1uart1-xfer 44uart1-cts4uart1-rts4uart2uart2-xfer 4 4##uart3uart3-xfer 44$$uart3-cts4uart3-rts4sd0sd0-clk4sd0-cmd 4sd0-cd4sd0-wp4sd0-bus-width1 4sd0-bus-width4@ 4 4 4 4sd1sd1-clk4sd1-cmd4sd1-cd4sd1-wp4sd1-bus-width14sd1-bus-width4@4444i2s0i2s0-bus44 4 4 4 4 444//i2s1i2s1-bus`44444411i2s2i2s2-bus`44444422lan8720aphy-int3  sdmmc-regulator,regulator-fixed sdmmc-supply-- 5 vsys-regulator,regulator-fixedvsysLK@LK@ #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1device_typeregrangesinterrupts#dma-cellsclocksclock-nameslinux,phandlestatusclock-frequency#clock-cellsclock-output-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaphysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthvmmc-supplyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsdmasdma-namesenable-methodnext-level-cacheoperating-pointsclock-latencyrockchip,playback-channelsrockchip,capture-channels#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsgpiostartup-delay-usvin-supply