*8'\(,'$$rockchip,rk3036-evbrockchip,rk3036&!7Rockchip RK3036 Evaluation boardchosenaliases=/i2c@20072000B/i2c@20056000G/i2c@2005a000L/dwmmc@1021c000R/dwmmc@10214000X/dwmmc@10218000^/serial@20060000f/serial@20064000n/serial@20068000memoryvmemory`@cpusrockchip,rk3036-smpcpu@f00vcpuarm,cortex-a7 sB@@cpu@f01vcpuarm,cortex-a7amba arm,amba-buspdma@20078000arm,pl330arm,primecell @ apb_pclkarm-pmuarm,cortex-a7-pmuLMtimerarm,armv7-timer 0   /n6oscillator fixed-clock/n6?xin24mR  bus_intmem@10080000 mmio-sram   smp-sram@0rockchip,rk3066-smp-sraminterrupt-controller@10139000 arm,gic-400_t     usb@101800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2 otgotg@@  disabledusb@101c00002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2 otghost disableddwmmc@102140000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc!@@/<4`<4`Dbiuciu  disableddwmmc@102180000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc!@<4` Eswbiuciuciu_drvciu_sample  disableddwmmc@1021c000rockchip,rk3288-dw-mshc!@ /<4`<4` Guybiuciuciu_drvciu_sample'2 7rx-txAN\fdefault t disabledi2s@10220000(rockchip,rk3036-i2srockchip,rk3066-i2s"@ 3i2s_hclki2s_clkR27txrxfdefaultt  disabledclock-controller@20000000rockchip,rk3036-cru ~ R#gsyscon@20008000rockchip,rk3036-grfsyscon   acodec-ana@20030000 rk3036-codec @~  acodec_pclkq disabledtimer@20044000,rockchip,rk3036-timerrockchip,rk3288-timer @   a timerpclkpwm@20050000(rockchip,rk3036-pwmrockchip,rk2928-pwm ^pwmfdefaultt  disabledpwm@20050010(rockchip,rk3036-pwmrockchip,rk2928-pwm ^pwmfdefaultt  disabledpwm@20050020(rockchip,rk3036-pwmrockchip,rk2928-pwm  ^pwmfdefaultt disabledpwm@20050030(rockchip,rk3036-pwmrockchip,rk2928-pwm 0^pwmfdefaultt disabledi2c@20056000rockchip,rk3288-i2c ` i2cMfdefaulttokayhym8563@51haoyu,hym8563QR/?xin32ki2c@2005a000rockchip,rk3288-i2c  i2cNfdefaultt disabledserial@20060000&rockchip,rk3036-uartsnps,dw-apb-uart  /n6MUbaudclkapb_pclkfdefault t disabledserial@20064000&rockchip,rk3036-uartsnps,dw-apb-uart @ /n6NVbaudclkapb_pclkfdefaultt disabledserial@20068000&rockchip,rk3036-uartsnps,dw-apb-uart  /n6OWbaudclkapb_pclkfdefaulttokayi2c@20072000rockchip,rk3288-i2c   i2cLfdefaultt disabledpinctrlrockchip,rk3036-pinctrl~ gpio0@2007c000rockchip,gpio-bank  $@_tgpio1@20080000rockchip,gpio-bank  %A_tgpio2@20084000rockchip,gpio-bank @ &B_tpcfg_pull_defaultpcfg-pull-nonepwm0pwm0-pin  pwm1pwm1-pin  pwm2pwm2-pinpwm3pwm3-pinsdmmcsdmmc-clksdmmc-cmdsdmcc-cdsdmmc-bus1sdmmc-bus4@sdiosdio-bus1 sdio-bus4@   sdio-cmdsdio-clk emmcemmc-clkemmc-cmdemmc-bus8i2c0i2c0-xfer i2c1i2c1-xfer i2c2i2c2-xfer i2si2s-bus`  uart0uart0-xfer uart0-ctsuart0-rtsuart1uart1-xfer uart2uart2-xfer  #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2mshc0mshc1mshc2serial0serial1serial2device_typeregenable-methodresetsoperating-pointsclock-latencyclockslinux,phandlerangesinterrupts#dma-cellsclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmastatusclock-freq-min-maxfifo-depthbroken-cdbus-widthcap-mmc-highspeeddefault-sample-phasedisable-wpdmasdma-namesmmc-ddr-1_8vnon-removablenum-slotspinctrl-namespinctrl-0rockchip,grf#reset-cellsassigned-clocksassigned-clock-rates#pwm-cellsreg-shiftreg-io-widthgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pins