=8(dti,omap3-ldpti,omap3&!7TI OMAP3430 LDP (Zoom1 Labrador)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000 d/displaymemorymmemoryycpuscpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmuarm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busyh l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-busy  pinmux@30 ti,omap3-padconfpinctrl-singley088>pinmux_twl4030_pinsFA8>pinmux_gpio_key_pinsHF8>pinmux_musb_pins`Frz|~vxt8>pinmux_mmc1_pins0F8>scm_conf@270sysconsimple-busyp0 p08>pbias_regulatorti,pbias-omap3ti,pbias-omapyZpbias_mmc_omap2430apbias_mmc_omap2430pw@-8>clocksmcbsp5_mux_fckti,composite-mux-clock}yh8>mcbsp5_fckti,composite-clock}mcbsp1_mux_fckti,composite-mux-clock}y8 > mcbsp1_fckti,composite-clock} mcbsp2_mux_fckti,composite-mux-clock} y8 > mcbsp2_fckti,composite-clock} mcbsp3_mux_fckti,composite-mux-clock} yh8>mcbsp3_fckti,composite-clock}mcbsp4_mux_fckti,composite-mux-clock} yh8>mcbsp4_fckti,composite-clock}clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \pinmux_twl4030_vpins F8>aes@480c5000 ti,omap3-aesaesyH PPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocksvirt_16_8m_ck fixed-clockY8>osc_sys_ck ti,mux-clock}y @8>sys_ckti,divider-clock}yp8>sys_clkout1ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}dpll3_m2x2_ckfixed-factor-clock}8>dpll4_x2_ckfixed-factor-clock}corex2_fckfixed-factor-clock}8>wkup_l4_ickfixed-factor-clock}8N>Ncorex2_d3_fckfixed-factor-clock}8>corex2_d5_fckfixed-factor-clock}8>clockdomainscm@48004000 ti,omap3-cmyH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock8@>@virt_12m_ck fixed-clock8>virt_13m_ck fixed-clock]@8>virt_19200000_ck fixed-clock$8>virt_26000000_ck fixed-clock8>virt_38_4m_ck fixed-clockI8>dpll4_ckti,omap3-dpll-per-clock}y D 08>dpll4_m2_ckti,divider-clock}?y H8 > dpll4_m2x2_mul_ckfixed-factor-clock} 8!>!dpll4_m2x2_ckti,gate-clock}!y 8">"omap_96m_alwon_fckfixed-factor-clock}"8)>)dpll3_ckti,omap3-dpll-core-clock}y @ 08>dpll3_m3_ckti,divider-clock}y@8#>#dpll3_m3x2_mul_ckfixed-factor-clock}#8$>$dpll3_m3x2_ckti,gate-clock}$ y 8%>%emu_core_alwon_ckfixed-factor-clock}%8b>bsys_altclk fixed-clock8.>.mcbsp_clks fixed-clock8>dpll3_m2_ckti,divider-clock}y @8>core_ckfixed-factor-clock}8&>&dpll1_fckti,divider-clock}&y @8'>'dpll1_ckti,omap3-dpll-clock}'y  $ @ 48>dpll1_x2_ckfixed-factor-clock}8(>(dpll1_x2m2_ckti,divider-clock}(y D8<><cm_96m_fckfixed-factor-clock})8*>*omap_96m_fck ti,mux-clock}*y @8E>Edpll4_m3_ckti,divider-clock} y@8+>+dpll4_m3x2_mul_ckfixed-factor-clock}+8,>,dpll4_m3x2_ckti,gate-clock},y 8->-omap_54m_fck ti,mux-clock}-.y @88>8cm_96m_d2_fckfixed-factor-clock}*8/>/omap_48m_fck ti,mux-clock}/.y @80>0omap_12m_fckfixed-factor-clock}08G>Gdpll4_m4_ckti,divider-clock} y@81>1dpll4_m4x2_mul_ckti,fixed-factor-clock}1&4A82>2dpll4_m4x2_ckti,gate-clock}2y A8>dpll4_m5_ckti,divider-clock}?y@83>3dpll4_m5x2_mul_ckti,fixed-factor-clock}3&4A84>4dpll4_m5x2_ckti,gate-clock}4y A8j>jdpll4_m6_ckti,divider-clock}?y@85>5dpll4_m6x2_mul_ckfixed-factor-clock}586>6dpll4_m6x2_ckti,gate-clock}6y 87>7emu_per_alwon_ckfixed-factor-clock}78c>cclkout2_src_gate_ck ti,composite-no-wait-gate-clock}&y p89>9clkout2_src_mux_ckti,composite-mux-clock}&*8y p8:>:clkout2_src_ckti,composite-clock}9:8;>;sys_clkout2ti,divider-clock};@y pTmpu_ckfixed-factor-clock}<8=>=arm_fckti,divider-clock}=y $emu_mpu_alwon_ckfixed-factor-clock}=8d>dl3_ickti,divider-clock}&y @8>>>l4_ickti,divider-clock}>y @8?>?rm_ickti,divider-clock}?y @gpt10_gate_fckti,composite-gate-clock} y 8A>Agpt10_mux_fckti,composite-mux-clock}@y @8B>Bgpt10_fckti,composite-clock}ABgpt11_gate_fckti,composite-gate-clock} y 8C>Cgpt11_mux_fckti,composite-mux-clock}@y @8D>Dgpt11_fckti,composite-clock}CDcore_96m_fckfixed-factor-clock}E8>mmchs2_fckti,wait-gate-clock}y 8>mmchs1_fckti,wait-gate-clock}y 8>i2c3_fckti,wait-gate-clock}y 8>i2c2_fckti,wait-gate-clock}y 8>i2c1_fckti,wait-gate-clock}y 8>mcbsp5_gate_fckti,composite-gate-clock} y 8>mcbsp1_gate_fckti,composite-gate-clock} y 8 > core_48m_fckfixed-factor-clock}08F>Fmcspi4_fckti,wait-gate-clock}Fy 8>mcspi3_fckti,wait-gate-clock}Fy 8>mcspi2_fckti,wait-gate-clock}Fy 8>mcspi1_fckti,wait-gate-clock}Fy 8>uart2_fckti,wait-gate-clock}Fy 8>uart1_fckti,wait-gate-clock}Fy  8>core_12m_fckfixed-factor-clock}G8H>Hhdq_fckti,wait-gate-clock}Hy 8>core_l3_ickfixed-factor-clock}>8I>Isdrc_ickti,wait-gate-clock}Iy 8>gpmc_fckfixed-factor-clock}Icore_l4_ickfixed-factor-clock}?8J>Jmmchs2_ickti,omap3-interface-clock}Jy 8>mmchs1_ickti,omap3-interface-clock}Jy 8>hdq_ickti,omap3-interface-clock}Jy 8>mcspi4_ickti,omap3-interface-clock}Jy 8>mcspi3_ickti,omap3-interface-clock}Jy 8>mcspi2_ickti,omap3-interface-clock}Jy 8>mcspi1_ickti,omap3-interface-clock}Jy 8>i2c3_ickti,omap3-interface-clock}Jy 8>i2c2_ickti,omap3-interface-clock}Jy 8>i2c1_ickti,omap3-interface-clock}Jy 8>uart2_ickti,omap3-interface-clock}Jy 8>uart1_ickti,omap3-interface-clock}Jy  8>gpt11_ickti,omap3-interface-clock}Jy  8>gpt10_ickti,omap3-interface-clock}Jy  8>mcbsp5_ickti,omap3-interface-clock}Jy  8>mcbsp1_ickti,omap3-interface-clock}Jy  8>omapctrl_ickti,omap3-interface-clock}Jy 8>dss_tv_fckti,gate-clock}8y8>dss_96m_fckti,gate-clock}Ey8>dss2_alwon_fckti,gate-clock}y8>dummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock}y 8K>Kgpt1_mux_fckti,composite-mux-clock}@y @8L>Lgpt1_fckti,composite-clock}KLaes2_ickti,omap3-interface-clock}Jy 8>wkup_32k_fckfixed-factor-clock}@8M>Mgpio1_dbckti,gate-clock}My 8>sha12_ickti,omap3-interface-clock}Jy 8>wdt2_fckti,wait-gate-clock}My 8>wdt2_ickti,omap3-interface-clock}Ny 8>wdt1_ickti,omap3-interface-clock}Ny 8>gpio1_ickti,omap3-interface-clock}Ny 8>omap_32ksync_ickti,omap3-interface-clock}Ny 8>gpt12_ickti,omap3-interface-clock}Ny 8>gpt1_ickti,omap3-interface-clock}Ny 8>per_96m_fckfixed-factor-clock})8 > per_48m_fckfixed-factor-clock}08O>Ouart3_fckti,wait-gate-clock}Oy 8>gpt2_gate_fckti,composite-gate-clock}y8P>Pgpt2_mux_fckti,composite-mux-clock}@y@8Q>Qgpt2_fckti,composite-clock}PQgpt3_gate_fckti,composite-gate-clock}y8R>Rgpt3_mux_fckti,composite-mux-clock}@y@8S>Sgpt3_fckti,composite-clock}RSgpt4_gate_fckti,composite-gate-clock}y8T>Tgpt4_mux_fckti,composite-mux-clock}@y@8U>Ugpt4_fckti,composite-clock}TUgpt5_gate_fckti,composite-gate-clock}y8V>Vgpt5_mux_fckti,composite-mux-clock}@y@8W>Wgpt5_fckti,composite-clock}VWgpt6_gate_fckti,composite-gate-clock}y8X>Xgpt6_mux_fckti,composite-mux-clock}@y@8Y>Ygpt6_fckti,composite-clock}XYgpt7_gate_fckti,composite-gate-clock}y8Z>Zgpt7_mux_fckti,composite-mux-clock}@y@8[>[gpt7_fckti,composite-clock}Z[gpt8_gate_fckti,composite-gate-clock} y8\>\gpt8_mux_fckti,composite-mux-clock}@y@8]>]gpt8_fckti,composite-clock}\]gpt9_gate_fckti,composite-gate-clock} y8^>^gpt9_mux_fckti,composite-mux-clock}@y@8_>_gpt9_fckti,composite-clock}^_per_32k_alwon_fckfixed-factor-clock}@8`>`gpio6_dbckti,gate-clock}`y8>gpio5_dbckti,gate-clock}`y8>gpio4_dbckti,gate-clock}`y8>gpio3_dbckti,gate-clock}`y8>gpio2_dbckti,gate-clock}`y 8>wdt3_fckti,wait-gate-clock}`y 8>per_l4_ickfixed-factor-clock}?8a>agpio6_ickti,omap3-interface-clock}ay8>gpio5_ickti,omap3-interface-clock}ay8>gpio4_ickti,omap3-interface-clock}ay8>gpio3_ickti,omap3-interface-clock}ay8>gpio2_ickti,omap3-interface-clock}ay 8>wdt3_ickti,omap3-interface-clock}ay 8>uart3_ickti,omap3-interface-clock}ay 8>uart4_ickti,omap3-interface-clock}ay8>gpt9_ickti,omap3-interface-clock}ay 8>gpt8_ickti,omap3-interface-clock}ay 8>gpt7_ickti,omap3-interface-clock}ay8>gpt6_ickti,omap3-interface-clock}ay8>gpt5_ickti,omap3-interface-clock}ay8>gpt4_ickti,omap3-interface-clock}ay8>gpt3_ickti,omap3-interface-clock}ay8>gpt2_ickti,omap3-interface-clock}ay8>mcbsp2_ickti,omap3-interface-clock}ay8>mcbsp3_ickti,omap3-interface-clock}ay8>mcbsp4_ickti,omap3-interface-clock}ay8>mcbsp2_gate_fckti,composite-gate-clock}y8 > mcbsp3_gate_fckti,composite-gate-clock}y8>mcbsp4_gate_fckti,composite-gate-clock}y8>emu_src_mux_ck ti,mux-clock}bcdy@8e>eemu_src_ckti,clkdm-gate-clock}e8f>fpclk_fckti,divider-clock}fy@pclkx2_fckti,divider-clock}fy@atclk_fckti,divider-clock}fy@traceclk_src_fck ti,mux-clock}bcdy@8g>gtraceclk_fckti,divider-clock}g y@secure_32k_fck fixed-clock8h>hgpt12_fckfixed-factor-clock}hwdt1_fckfixed-factor-clock}hsecurity_l4_ick2fixed-factor-clock}?8i>iaes1_ickti,omap3-interface-clock}iy rng_ickti,omap3-interface-clock}iy sha11_ickti,omap3-interface-clock}iy des1_ickti,omap3-interface-clock}iy cam_mclkti,gate-clock}jyAcam_ick!ti,omap3-no-wait-interface-clock}?y8>csi2_96m_fckti,gate-clock}y8>security_l3_ickfixed-factor-clock}>8k>kpka_ickti,omap3-interface-clock}ky icr_ickti,omap3-interface-clock}Jy des2_ickti,omap3-interface-clock}Jy mspro_ickti,omap3-interface-clock}Jy mailboxes_ickti,omap3-interface-clock}Jy ssi_l4_ickfixed-factor-clock}?8r>rsr1_fckti,wait-gate-clock}y sr2_fckti,wait-gate-clock}y sr_l4_ickfixed-factor-clock}?dpll2_fckti,divider-clock}&y@8l>ldpll2_ckti,omap3-dpll-clock}ly$@4j|8m>mdpll2_m2_ckti,divider-clock}myD8n>niva2_ckti,wait-gate-clock}ny8>modem_fckti,omap3-interface-clock}y 8>sad2d_ickti,omap3-interface-clock}>y 8>mad2d_ickti,omap3-interface-clock}>y 8>mspro_fckti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock}y 8o>ossi_ssr_div_fck_3430es2ti,composite-divider-clock}y @$8p>pssi_ssr_fck_3430es2ti,composite-clock}op8q>qssi_sst_fck_3430es2fixed-factor-clock}q8>hsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clock}Iy 8>ssi_ick_3430es2ti,omap3-ssi-interface-clock}ry 8>usim_gate_fckti,composite-gate-clock}E y 8}>}sys_d2_ckfixed-factor-clock}8t>tomap_96m_d2_fckfixed-factor-clock}E8u>uomap_96m_d4_fckfixed-factor-clock}E8v>vomap_96m_d8_fckfixed-factor-clock}E8w>womap_96m_d10_fckfixed-factor-clock}E 8x>xdpll5_m2_d4_ckfixed-factor-clock}s8y>ydpll5_m2_d8_ckfixed-factor-clock}s8z>zdpll5_m2_d16_ckfixed-factor-clock}s8{>{dpll5_m2_d20_ckfixed-factor-clock}s8|>|usim_mux_fckti,composite-mux-clock(}tuvwxyz{|y @8~>~usim_fckti,composite-clock}}~usim_ickti,omap3-interface-clock}Ny  8>dpll5_ckti,omap3-dpll-clock}y  $ L 4j|8>dpll5_m2_ckti,divider-clock}y P8s>ssgx_gate_fckti,composite-gate-clock}&y 8>core_d3_ckfixed-factor-clock}&8>core_d4_ckfixed-factor-clock}&8>core_d6_ckfixed-factor-clock}&8>omap_192m_alwon_fckfixed-factor-clock}"8>core_d2_ckfixed-factor-clock}&8>sgx_mux_fckti,composite-mux-clock }*y @8>sgx_fckti,composite-clock}sgx_ickti,wait-gate-clock}>y 8>cpefuse_fckti,gate-clock}y 8>ts_fckti,gate-clock}@y 8>usbtll_fckti,wait-gate-clock}sy 8>usbtll_ickti,omap3-interface-clock}Jy 8>mmchs3_ickti,omap3-interface-clock}Jy 8>mmchs3_fckti,wait-gate-clock}y 8>dss1_alwon_fck_3430es2ti,dss-gate-clock}yA8>dss_ick_3430es2ti,omap3-dss-interface-clock}?y8>usbhost_120m_fckti,gate-clock}sy8>usbhost_48m_fckti,dss-gate-clock}0y8>usbhost_ickti,omap3-dss-interface-clock}?y8>clockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}fdpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}md2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }counter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH 8>dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH`  `8>gpio@48310000ti,omap3-gpioyH1gpio1gpio@49050000ti,omap3-gpioyIgpio28>gpio@49052000ti,omap3-gpioyI gpio3gpio@49054000ti,omap3-gpioyI@ gpio48>gpio@49056000ti,omap3-gpioyI`!gpio58>gpio@49058000ti,omap3-gpioyI"gpio6serial@4806a000ti,omap3-uartyH H12txrxuart1lserial@4806c000ti,omap3-uartyHI34txrxuart2lserial@49020000ti,omap3-uartyIJn56txrxuart3li2c@48070000 ti,omap3-i2cyH8txrxi2c1'@twl@48yH& ti,twl4030 defaultpowerti,twl4030-power-idle#rtcti,twl4030-rtc bciti,twl4030-bci 3watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1avccregulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1p ' 8>regulator-vdacti,twl4030-vdacpw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1p:08>regulator-vmmc2ti,twl4030-vmmc2p:0regulator-vusb1v5ti,twl4030-vusb1v58>regulator-vusb1v8ti,twl4030-vusb1v88>regulator-vusb3v1ti,twl4030-vusb3v18>regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2pw@w@Aregulator-vsimti,twl4030-vsimpw@-gpioti,twl4030-gpio8>twl4030-usbti,twl4030-usb Ucq8>pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadD?  @A Bsrmadcti,twl4030-madci2c@48072000 ti,omap3-i2cyH 9txrxi2c2i2c@48060000 ti,omap3-i2cyH=txrxi2c3mailbox@48094000ti,omap3-mailboxmailboxyH @dsp  spi@48098000ti,omap2-mcspiyH Amcspi1&@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3tsc2046@0y ti,tsc20464B@FQZ@clu(& spi@4809a000ti,omap2-mcspiyH Bmcspi2& +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [mcspi3& tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiyH 0mcspi4&FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-pre-es3-hsmmcyH Smmc1=>txrx defaultmmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrx disabledmmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_isp8>mmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrx)mcbsp1 txrx disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetone)mcbsp2mcbsp2_sidetone!"txrx disabledmcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetone)mcbsp3mcbsp3_sidetonetxrx disabledmcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrx)mcbsp4txrx disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrx)mcbsp5txrx disabledsham@480c3000ti,omap3-shamshamyH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreyH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivayH timer@48318000ti,omap3430-timeryH1%timer18timer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5Gtimer@4903a000ti,omap3430-timeryI*timer6Gtimer@4903c000ti,omap3430-timeryI+timer7Gtimer@4903e000ti,omap3430-timeryI,timer8TGtimer@49040000ti,omap3430-timeryI-timer9Ttimer@48086000ti,omap3430-timeryH`.timer10Ttimer@48088000ti,omap3430-timeryH/timer11Ttimer@48304000ti,omap3430-timeryH0@_timer128ausbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hsohci@48064400ti,ohci-omap3yHD&Lehci@48064800 ti,ehci-omapyHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcynrxtxq} ethernet@gpmcsmsc,lan9221smsc,lan9115!4(G-Ud-rxKK,DVft& ynand@0,0 micron,nand ybch8,,!"4,r(U6@RRD(,partition@0 X-Loaderypartition@80000U-Bootypartition@1c0000 Environmentypartition@200000Kernely partition@2000000 Filesystemyusb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hs  default2dss@48050000 ti,omap3-dssyHok dss_core}fckdispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpoint%8>ssi-controller@48058000 ti,omap3-ssissiokyHHsysgddGgdd_mpu }q ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrx&CDssi-port@4805b000ti,omap3-ssi-portyHHtxrx&EFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$isp@480bc000 ti,omap3-ispyH H |0Z7portsregulator-vddvarioregulator-fixed avddvarioA8>regulator-vdd33aregulator-fixedavdd33aA8>gpio_keys gpio-keys defaultkey_enterenter CIkey_f1f1 CI;key_f2f2 CI<key_f3f3 CI=key_f4f4 C I>key_leftleft C Iikey_rightright C Ijkey_upup C Igkey_downdown C Ilbacklightgpio-backlightT Cregulator-lcd-3v3regulator-fixedalcd_3v3p2Z2Z_pA8>displaysharp,ls037v7dw01lcdp }  portendpoint8> #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,use_poweroffbci3v1-supplyregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplybus-widthstatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phypowerremote-endpointdata-linesiommusti,phy-typegpioslinux,codedefault-onstartup-delay-uspower-supplyenable-gpiosreset-gpiosmode-gpios