8d(+,)isee,omap3-igep0030ti,omap36xxti,omap3&*7IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@49042000memorylmemoryx cpuscpu@0arm,cortex-a8lcpux|cpus 'O 57pmuarm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busxh l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-busx  pinmux@30 ti,omap3-padconfpinctrl-singlex08pinmux_uart1_pins+RL?Epinmux_uart3_pins+np?Epinmux_mcbsp2_pins + ?Epinmux_mmc1_pins0+?Epinmux_mmc2_pins0+(*,.02?Epinmux_i2c1_pins+?Epinmux_i2c3_pins+?Epinmux_twl4030_pins+A?Epinmux_uart2_pins +<>@B?Epinmux_lbee1usjyc_pins+68:?Escm_conf@270sysconsimple-busxp0 p0?Epbias_regulatorti,pbias-omap3ti,pbias-omapxMpbias_mmc_omap2430Tpbias_mmc_omap2430cw@{-?Eclocksmcbsp5_mux_fckti,composite-mux-clock|xh?Emcbsp5_fckti,composite-clock|mcbsp1_mux_fckti,composite-mux-clock|x? E mcbsp1_fckti,composite-clock| mcbsp2_mux_fckti,composite-mux-clock| x? E mcbsp2_fckti,composite-clock| mcbsp3_mux_fckti,composite-mux-clock| xh?Emcbsp3_fckti,composite-clock| mcbsp4_mux_fckti,composite-mux-clock| xh?Emcbsp4_fckti,composite-clock|clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \pinmux_twl4030_vpins +?Eaes@480c5000 ti,omap3-aesaesxH PPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocksvirt_16_8m_ck fixed-clockY?Eosc_sys_ck ti,mux-clock|x @?Esys_ckti,divider-clock|xp?Esys_clkout1ti,gate-clock|x pdpll3_x2_ckfixed-factor-clock|dpll3_m2x2_ckfixed-factor-clock|?Edpll4_x2_ckfixed-factor-clock|corex2_fckfixed-factor-clock|?Ewkup_l4_ickfixed-factor-clock|?MEMcorex2_d3_fckfixed-factor-clock|?Ecorex2_d5_fckfixed-factor-clock|?Eclockdomainscm@48004000 ti,omap3-cmxH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock??E?virt_12m_ck fixed-clock?Evirt_13m_ck fixed-clock]@?Evirt_19200000_ck fixed-clock$?Evirt_26000000_ck fixed-clock?Evirt_38_4m_ck fixed-clockI?Edpll4_ckti,omap3-dpll-per-j-type-clock|x D 0?Edpll4_m2_ckti,divider-clock|?x H?Edpll4_m2x2_mul_ckfixed-factor-clock|? E dpll4_m2x2_ckti,hsdiv-gate-clock| x ?!E!omap_96m_alwon_fckfixed-factor-clock|!?(E(dpll3_ckti,omap3-dpll-core-clock|x @ 0?Edpll3_m3_ckti,divider-clock|x@?"E"dpll3_m3x2_mul_ckfixed-factor-clock|"?#E#dpll3_m3x2_ckti,hsdiv-gate-clock|# x ?$E$emu_core_alwon_ckfixed-factor-clock|$?aEasys_altclk fixed-clock?-E-mcbsp_clks fixed-clock?Edpll3_m2_ckti,divider-clock|x @?Ecore_ckfixed-factor-clock|?%E%dpll1_fckti,divider-clock|%x @?&E&dpll1_ckti,omap3-dpll-clock|&x  $ @ 4?Edpll1_x2_ckfixed-factor-clock|?'E'dpll1_x2m2_ckti,divider-clock|'x D?;E;cm_96m_fckfixed-factor-clock|(?)E)omap_96m_fck ti,mux-clock|)x @?DEDdpll4_m3_ckti,divider-clock| x@?*E*dpll4_m3x2_mul_ckfixed-factor-clock|*?+E+dpll4_m3x2_ckti,hsdiv-gate-clock|+x ?,E,omap_54m_fck ti,mux-clock|,-x @?7E7cm_96m_d2_fckfixed-factor-clock|)?.E.omap_48m_fck ti,mux-clock|.-x @?/E/omap_12m_fckfixed-factor-clock|/?FEFdpll4_m4_ckti,divider-clock| x@?0E0dpll4_m4x2_mul_ckti,fixed-factor-clock|0'4?1E1dpll4_m4x2_ckti,gate-clock|1x 4?Edpll4_m5_ckti,divider-clock|?x@?2E2dpll4_m5x2_mul_ckti,fixed-factor-clock|2'4?3E3dpll4_m5x2_ckti,hsdiv-gate-clock|3x 4?iEidpll4_m6_ckti,divider-clock|?x@?4E4dpll4_m6x2_mul_ckfixed-factor-clock|4?5E5dpll4_m6x2_ckti,hsdiv-gate-clock|5x ?6E6emu_per_alwon_ckfixed-factor-clock|6?bEbclkout2_src_gate_ck ti,composite-no-wait-gate-clock|%x p?8E8clkout2_src_mux_ckti,composite-mux-clock|%)7x p?9E9clkout2_src_ckti,composite-clock|89?:E:sys_clkout2ti,divider-clock|:@x pGmpu_ckfixed-factor-clock|;?<E<arm_fckti,divider-clock|<x $emu_mpu_alwon_ckfixed-factor-clock|<?cEcl3_ickti,divider-clock|%x @?=E=l4_ickti,divider-clock|=x @?>E>rm_ickti,divider-clock|>x @gpt10_gate_fckti,composite-gate-clock| x ?@E@gpt10_mux_fckti,composite-mux-clock|?x @?AEAgpt10_fckti,composite-clock|@Agpt11_gate_fckti,composite-gate-clock| x ?BEBgpt11_mux_fckti,composite-mux-clock|?x @?CECgpt11_fckti,composite-clock|BCcore_96m_fckfixed-factor-clock|D?Emmchs2_fckti,wait-gate-clock|x ?Emmchs1_fckti,wait-gate-clock|x ?Ei2c3_fckti,wait-gate-clock|x ?Ei2c2_fckti,wait-gate-clock|x ?Ei2c1_fckti,wait-gate-clock|x ?Emcbsp5_gate_fckti,composite-gate-clock| x ?Emcbsp1_gate_fckti,composite-gate-clock| x ?Ecore_48m_fckfixed-factor-clock|/?EEEmcspi4_fckti,wait-gate-clock|Ex ?Emcspi3_fckti,wait-gate-clock|Ex ?Emcspi2_fckti,wait-gate-clock|Ex ?Emcspi1_fckti,wait-gate-clock|Ex ?Euart2_fckti,wait-gate-clock|Ex ?Euart1_fckti,wait-gate-clock|Ex  ?Ecore_12m_fckfixed-factor-clock|F?GEGhdq_fckti,wait-gate-clock|Gx ?Ecore_l3_ickfixed-factor-clock|=?HEHsdrc_ickti,wait-gate-clock|Hx ?Egpmc_fckfixed-factor-clock|Hcore_l4_ickfixed-factor-clock|>?IEImmchs2_ickti,omap3-interface-clock|Ix ?Emmchs1_ickti,omap3-interface-clock|Ix ?Ehdq_ickti,omap3-interface-clock|Ix ?Emcspi4_ickti,omap3-interface-clock|Ix ?Emcspi3_ickti,omap3-interface-clock|Ix ?Emcspi2_ickti,omap3-interface-clock|Ix ?Emcspi1_ickti,omap3-interface-clock|Ix ?Ei2c3_ickti,omap3-interface-clock|Ix ?Ei2c2_ickti,omap3-interface-clock|Ix ?Ei2c1_ickti,omap3-interface-clock|Ix ?Euart2_ickti,omap3-interface-clock|Ix ?Euart1_ickti,omap3-interface-clock|Ix  ?Egpt11_ickti,omap3-interface-clock|Ix  ?Egpt10_ickti,omap3-interface-clock|Ix  ?Emcbsp5_ickti,omap3-interface-clock|Ix  ?Emcbsp1_ickti,omap3-interface-clock|Ix  ?Eomapctrl_ickti,omap3-interface-clock|Ix ?Edss_tv_fckti,gate-clock|7x?Edss_96m_fckti,gate-clock|Dx?Edss2_alwon_fckti,gate-clock|x?Edummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock|x ?JEJgpt1_mux_fckti,composite-mux-clock|?x @?KEKgpt1_fckti,composite-clock|JKaes2_ickti,omap3-interface-clock|Ix ?Ewkup_32k_fckfixed-factor-clock|??LELgpio1_dbckti,gate-clock|Lx ?Esha12_ickti,omap3-interface-clock|Ix ?Ewdt2_fckti,wait-gate-clock|Lx ?Ewdt2_ickti,omap3-interface-clock|Mx ?Ewdt1_ickti,omap3-interface-clock|Mx ?Egpio1_ickti,omap3-interface-clock|Mx ?Eomap_32ksync_ickti,omap3-interface-clock|Mx ?Egpt12_ickti,omap3-interface-clock|Mx ?Egpt1_ickti,omap3-interface-clock|Mx ?Eper_96m_fckfixed-factor-clock|(? E per_48m_fckfixed-factor-clock|/?NENuart3_fckti,wait-gate-clock|Nx ?Egpt2_gate_fckti,composite-gate-clock|x?OEOgpt2_mux_fckti,composite-mux-clock|?x@?PEPgpt2_fckti,composite-clock|OPgpt3_gate_fckti,composite-gate-clock|x?QEQgpt3_mux_fckti,composite-mux-clock|?x@?RERgpt3_fckti,composite-clock|QRgpt4_gate_fckti,composite-gate-clock|x?SESgpt4_mux_fckti,composite-mux-clock|?x@?TETgpt4_fckti,composite-clock|STgpt5_gate_fckti,composite-gate-clock|x?UEUgpt5_mux_fckti,composite-mux-clock|?x@?VEVgpt5_fckti,composite-clock|UVgpt6_gate_fckti,composite-gate-clock|x?WEWgpt6_mux_fckti,composite-mux-clock|?x@?XEXgpt6_fckti,composite-clock|WXgpt7_gate_fckti,composite-gate-clock|x?YEYgpt7_mux_fckti,composite-mux-clock|?x@?ZEZgpt7_fckti,composite-clock|YZgpt8_gate_fckti,composite-gate-clock| x?[E[gpt8_mux_fckti,composite-mux-clock|?x@?\E\gpt8_fckti,composite-clock|[\gpt9_gate_fckti,composite-gate-clock| x?]E]gpt9_mux_fckti,composite-mux-clock|?x@?^E^gpt9_fckti,composite-clock|]^per_32k_alwon_fckfixed-factor-clock|??_E_gpio6_dbckti,gate-clock|_x?Egpio5_dbckti,gate-clock|_x?Egpio4_dbckti,gate-clock|_x?Egpio3_dbckti,gate-clock|_x?Egpio2_dbckti,gate-clock|_x ?Ewdt3_fckti,wait-gate-clock|_x ?Eper_l4_ickfixed-factor-clock|>?`E`gpio6_ickti,omap3-interface-clock|`x?Egpio5_ickti,omap3-interface-clock|`x?Egpio4_ickti,omap3-interface-clock|`x?Egpio3_ickti,omap3-interface-clock|`x?Egpio2_ickti,omap3-interface-clock|`x ?Ewdt3_ickti,omap3-interface-clock|`x ?Euart3_ickti,omap3-interface-clock|`x ?Euart4_ickti,omap3-interface-clock|`x?Egpt9_ickti,omap3-interface-clock|`x ?Egpt8_ickti,omap3-interface-clock|`x ?Egpt7_ickti,omap3-interface-clock|`x?Egpt6_ickti,omap3-interface-clock|`x?Egpt5_ickti,omap3-interface-clock|`x?Egpt4_ickti,omap3-interface-clock|`x?Egpt3_ickti,omap3-interface-clock|`x?Egpt2_ickti,omap3-interface-clock|`x?Emcbsp2_ickti,omap3-interface-clock|`x?Emcbsp3_ickti,omap3-interface-clock|`x?Emcbsp4_ickti,omap3-interface-clock|`x?Emcbsp2_gate_fckti,composite-gate-clock|x? E mcbsp3_gate_fckti,composite-gate-clock|x? E mcbsp4_gate_fckti,composite-gate-clock|x?Eemu_src_mux_ck ti,mux-clock|abcx@?dEdemu_src_ckti,clkdm-gate-clock|d?eEepclk_fckti,divider-clock|ex@pclkx2_fckti,divider-clock|ex@atclk_fckti,divider-clock|ex@traceclk_src_fck ti,mux-clock|abcx@?fEftraceclk_fckti,divider-clock|f x@secure_32k_fck fixed-clock?gEggpt12_fckfixed-factor-clock|gwdt1_fckfixed-factor-clock|gsecurity_l4_ick2fixed-factor-clock|>?hEhaes1_ickti,omap3-interface-clock|hx rng_ickti,omap3-interface-clock|hx sha11_ickti,omap3-interface-clock|hx des1_ickti,omap3-interface-clock|hx cam_mclkti,gate-clock|ix4cam_ick!ti,omap3-no-wait-interface-clock|>x?Ecsi2_96m_fckti,gate-clock|x?Esecurity_l3_ickfixed-factor-clock|=?jEjpka_ickti,omap3-interface-clock|jx icr_ickti,omap3-interface-clock|Ix des2_ickti,omap3-interface-clock|Ix mspro_ickti,omap3-interface-clock|Ix mailboxes_ickti,omap3-interface-clock|Ix ssi_l4_ickfixed-factor-clock|>?qEqsr1_fckti,wait-gate-clock|x sr2_fckti,wait-gate-clock|x sr_l4_ickfixed-factor-clock|>dpll2_fckti,divider-clock|%x@?kEkdpll2_ckti,omap3-dpll-clock|kx$@4]ow?lEldpll2_m2_ckti,divider-clock|lxD?mEmiva2_ckti,wait-gate-clock|mx?Emodem_fckti,omap3-interface-clock|x ?Esad2d_ickti,omap3-interface-clock|=x ?Emad2d_ickti,omap3-interface-clock|=x ?Emspro_fckti,wait-gate-clock|x ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock|x ?nEnssi_ssr_div_fck_3430es2ti,composite-divider-clock|x @$?oEossi_ssr_fck_3430es2ti,composite-clock|no?pEpssi_sst_fck_3430es2fixed-factor-clock|p?Ehsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clock|Hx ?Essi_ick_3430es2ti,omap3-ssi-interface-clock|qx ?Eusim_gate_fckti,composite-gate-clock|D x ?|E|sys_d2_ckfixed-factor-clock|?sEsomap_96m_d2_fckfixed-factor-clock|D?tEtomap_96m_d4_fckfixed-factor-clock|D?uEuomap_96m_d8_fckfixed-factor-clock|D?vEvomap_96m_d10_fckfixed-factor-clock|D ?wEwdpll5_m2_d4_ckfixed-factor-clock|r?xExdpll5_m2_d8_ckfixed-factor-clock|r?yEydpll5_m2_d16_ckfixed-factor-clock|r?zEzdpll5_m2_d20_ckfixed-factor-clock|r?{E{usim_mux_fckti,composite-mux-clock(|stuvwxyz{x @?}E}usim_fckti,composite-clock||}usim_ickti,omap3-interface-clock|Mx  ?Edpll5_ckti,omap3-dpll-clock|x  $ L 4]o?~E~dpll5_m2_ckti,divider-clock|~x P?rErsgx_gate_fckti,composite-gate-clock|%x ?Ecore_d3_ckfixed-factor-clock|%?Ecore_d4_ckfixed-factor-clock|%?Ecore_d6_ckfixed-factor-clock|%?Eomap_192m_alwon_fckfixed-factor-clock|!?Ecore_d2_ckfixed-factor-clock|%?Esgx_mux_fckti,composite-mux-clock |)x @?Esgx_fckti,composite-clock|sgx_ickti,wait-gate-clock|=x ?Ecpefuse_fckti,gate-clock|x ?Ets_fckti,gate-clock|?x ?Eusbtll_fckti,wait-gate-clock|rx ?Eusbtll_ickti,omap3-interface-clock|Ix ?Emmchs3_ickti,omap3-interface-clock|Ix ?Emmchs3_fckti,wait-gate-clock|x ?Edss1_alwon_fck_3430es2ti,dss-gate-clock|x4?Edss_ick_3430es2ti,omap3-dss-interface-clock|>x?Eusbhost_120m_fckti,gate-clock|rx?Eusbhost_48m_fckti,dss-gate-clock|/x?Eusbhost_ickti,omap3-dss-interface-clock|>x?Euart4_fckti,wait-gate-clock|Nx?Eclockdomainscore_l3_clkdmti,clockdomain|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|edpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|ld2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|~sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH ?Edma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH`  `?Egpio@48310000ti,omap3-gpioxH1gpio1?Egpio@49050000ti,omap3-gpioxIgpio2gpio@49052000ti,omap3-gpioxI gpio3gpio@49054000ti,omap3-gpioxI@ gpio4gpio@49056000ti,omap3-gpioxI`!gpio5?Egpio@49058000ti,omap3-gpioxI"gpio6serial@4806a000ti,omap3-uartxH H12txrxuart1ldefault serial@4806c000ti,omap3-uartxHI34txrxuart2ldefault serial@49020000ti,omap3-uartxIJ56txrxuart3ldefault i2c@48070000 ti,omap3-i2cxH8txrxi2c1default '@twl@48xH& ti,twl4030default audioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1c '{ regulator-vdacti,twl4030-vdaccw@{w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1c:{0?Eregulator-vmmc2ti,twl4030-vmmc2c:{0regulator-vusb1v5ti,twl4030-vusb1v5?Eregulator-vusb1v8ti,twl4030-vusb1v8?Eregulator-vusb3v1ti,twl4030-vusb3v1?Eregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2cw@{w@regulator-vsimti,twl4030-vsimcw@{-?Egpioti,twl4030-gpio$?Etwl4030-usbti,twl4030-usb 0>LZc?Epwmti,twl4030-pwmnpwmledti,twl4030-pwmlednpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadymadcti,twl4030-madci2c@48072000 ti,omap3-i2cxH 9txrxi2c2i2c@48060000 ti,omap3-i2cxH=txrxi2c3default mailbox@48094000ti,omap3-mailboxmailboxxH @dsp  spi@48098000ti,omap2-mcspixH Amcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH Bmcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0mcspi4FGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1=>txrxdefault (8mmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrxdefault B8Mmmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx [disabledmmu@480bd400bti,omap2-iommuxH mmu_ispo?Emmu@5d000000bti,omap2-iommux]mmu_iva [disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@mpu ;< commontxrxmcbsp1 txrx [disabledmcbsp@49022000ti,omap3-mcbspxI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx[okaydefault ?Emcbsp@49024000ti,omap3-mcbspxI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx [disabledmcbsp@49026000ti,omap3-mcbspxI`mpu 67 commontxrxmcbsp4txrx [disabledmcbsp@48096000ti,omap3-mcbspxH `mpu QR commontxrxmcbsp5txrx [disabledsham@480c3000ti,omap3-shamshamxH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH timer@48318000ti,omap3430-timerxH1%timer1timer@49032000ti,omap3430-timerxI &timer2timer@49034000ti,omap3430-timerxI@'timer3timer@49036000ti,omap3430-timerxI`(timer4timer@49038000ti,omap3430-timerxI)timer5timer@4903a000ti,omap3430-timerxI*timer6timer@4903c000ti,omap3430-timerxI+timer7timer@4903e000ti,omap3430-timerxI,timer8timer@49040000ti,omap3430-timerxI-timer9timer@48086000ti,omap3430-timerxH`.timer10timer@48088000ti,omap3430-timerxH/timer11timer@48304000ti,omap3430-timerxH0@_timer12usbhstll@48062000 ti,usbhs-tllxH N usb_tll_hsusbhshost@48064000ti,usbhs-hostxH@ usb_host_hsohci@48064400ti,ohci-omap3xHD&Lehci@48064800 ti,ehci-omapxHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcxnrxtxnand@0,0micron,mt29c4g96maz x/bch8?P^,p,",(6@RR(partition@00SPLxpartition@800000U-Bootxpartition@1c0000 0Environmentx(partition@2800000Kernelx80partition@780000 0Filesystemxhusb_otg_hs@480ab000ti,omap3-musbxH \]mcdma usb_otg_hs6AI Rai nusb2-phy^x2dss@48050000 ti,omap3-dssxH [disabled dss_core|fckdispc@48050400ti,omap3-dispcxH dss_dispc|fckencoder@4804fc00 ti,omap3-dsixHH@H protophypll [disabled dss_dsi1| fcksys_clkencoder@48050800ti,omap3-rfbixH [disabled dss_rfbi|fckickencoder@48050c00ti,omap3-vencxH  [disabled dss_venc|fcktv_dac_clkssi-controller@48058000 ti,omap3-ssissi[okxHHsysgddGgdd_mpu |p ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portxHHtxrx&CDssi-port@4805b000ti,omap3-ssi-portxHHtxrx&EFserial@49042000ti,omap3-uartxI PQRtxrxuart4lregulator-abb-mpu ti,abb-v1 Tabb_mpu_iva~xH0rH0hbase-addressint-address|`sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singlexH%\pinmux_leds_core2_pins+@?Eisp@480bc000 ti,omap3-ispxH H Mportssoundti,omap-twl4030igep2regulator-vdd33regulator-fixedTvdd33gpio_leds gpio-ledsdefault user00omap3:red:user0  offuser10omap3:green:user1  offuser20omap3:red:user1  offboot0omap3:green:boot  onfixedregulator-mmcsdioregulator-fixedTvmmcsdio_fixedc2Z{2Z?Emmc2_pwrseqmmc-pwrseq-simple  ?E #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthmmc-pwrseqnon-removablestatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespower#address-cellti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-typeti,modelti,mcbspregulator-always-ongpiosdefault-statereset-gpios