8Ӥ(#lteejet,mt_ventouxti,omap3&7TeeJet Mt.Ventouxchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000memorydmemorypcpuscpu@0arm,cortex-a8dcpupt{cpu(HАg8 Odp` 'ppmuarm,cortex-a8-pmupTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busph l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-busp  pinmux@30 ti,omap3-padconfpinctrl-singlep08 scm_conf@270sysconsimple-buspp0 p0*0pbias_regulatorti,pbias-omap3ti,pbias-omapp8pbias_mmc_omap2430?pbias_mmc_omap2430Nw@f-*0clocksmcbsp5_mux_fck~ti,composite-mux-clocktph*0mcbsp5_fck~ti,composite-clocktmcbsp1_mux_fck~ti,composite-mux-clocktp* 0 mcbsp1_fck~ti,composite-clockt mcbsp2_mux_fck~ti,composite-mux-clockt p* 0 mcbsp2_fck~ti,composite-clockt mcbsp3_mux_fck~ti,composite-mux-clockt ph*0mcbsp3_fck~ti,composite-clockt mcbsp4_mux_fck~ti,composite-mux-clockt ph*0mcbsp4_fck~ti,composite-clocktclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlep \ aes@480c5000 ti,omap3-aesaespH PPABtxrxprm@48306000 ti,omap3-prmpH0`@ clocksvirt_16_8m_ck~ fixed-clockY*0osc_sys_ck~ ti,mux-clocktp @*0sys_ck~ti,divider-clocktpp*0sys_clkout1~ti,gate-clocktp pdpll3_x2_ck~fixed-factor-clocktdpll3_m2x2_ck~fixed-factor-clockt*0dpll4_x2_ck~fixed-factor-clocktcorex2_fck~fixed-factor-clockt*0wkup_l4_ick~fixed-factor-clockt*M0Mcorex2_d3_fck~fixed-factor-clockt*0corex2_d5_fck~fixed-factor-clockt*0clockdomainscm@48004000 ti,omap3-cmpH@@clocksdummy_apb_pclk~ fixed-clockomap_32k_fck~ fixed-clock*?0?virt_12m_ck~ fixed-clock*0virt_13m_ck~ fixed-clock]@*0virt_19200000_ck~ fixed-clock$*0virt_26000000_ck~ fixed-clock*0virt_38_4m_ck~ fixed-clockI*0dpll4_ck~ti,omap3-dpll-per-clocktp D 0*0dpll4_m2_ck~ti,divider-clockt?p H*0dpll4_m2x2_mul_ck~fixed-factor-clockt* 0 dpll4_m2x2_ck~ti,gate-clockt p *!0!omap_96m_alwon_fck~fixed-factor-clockt!*(0(dpll3_ck~ti,omap3-dpll-core-clocktp @ 0*0dpll3_m3_ck~ti,divider-clocktp@*"0"dpll3_m3x2_mul_ck~fixed-factor-clockt"*#0#dpll3_m3x2_ck~ti,gate-clockt# p *$0$emu_core_alwon_ck~fixed-factor-clockt$*a0asys_altclk~ fixed-clock*-0-mcbsp_clks~ fixed-clock*0dpll3_m2_ck~ti,divider-clocktp @*0core_ck~fixed-factor-clockt*%0%dpll1_fck~ti,divider-clockt%p @*&0&dpll1_ck~ti,omap3-dpll-clockt&p  $ @ 4*0dpll1_x2_ck~fixed-factor-clockt*'0'dpll1_x2m2_ck~ti,divider-clockt'p D*;0;cm_96m_fck~fixed-factor-clockt(*)0)omap_96m_fck~ ti,mux-clockt)p @*D0Ddpll4_m3_ck~ti,divider-clockt p@**0*dpll4_m3x2_mul_ck~fixed-factor-clockt**+0+dpll4_m3x2_ck~ti,gate-clockt+p *,0,omap_54m_fck~ ti,mux-clockt,-p @*707cm_96m_d2_fck~fixed-factor-clockt)*.0.omap_48m_fck~ ti,mux-clockt.-p @*/0/omap_12m_fck~fixed-factor-clockt/*F0Fdpll4_m4_ck~ti,divider-clockt p@*000dpll4_m4x2_mul_ck~ti,fixed-factor-clockt0*101dpll4_m4x2_ck~ti,gate-clockt1p *0dpll4_m5_ck~ti,divider-clockt?p@*202dpll4_m5x2_mul_ck~ti,fixed-factor-clockt2*303dpll4_m5x2_ck~ti,gate-clockt3p *i0idpll4_m6_ck~ti,divider-clockt?p@*404dpll4_m6x2_mul_ck~fixed-factor-clockt4*505dpll4_m6x2_ck~ti,gate-clockt5p *606emu_per_alwon_ck~fixed-factor-clockt6*b0bclkout2_src_gate_ck~ ti,composite-no-wait-gate-clockt%p p*808clkout2_src_mux_ck~ti,composite-mux-clockt%)7p p*909clkout2_src_ck~ti,composite-clockt89*:0:sys_clkout2~ti,divider-clockt:@p p2mpu_ck~fixed-factor-clockt;*<0<arm_fck~ti,divider-clockt<p $emu_mpu_alwon_ck~fixed-factor-clockt<*c0cl3_ick~ti,divider-clockt%p @*=0=l4_ick~ti,divider-clockt=p @*>0>rm_ick~ti,divider-clockt>p @gpt10_gate_fck~ti,composite-gate-clockt p *@0@gpt10_mux_fck~ti,composite-mux-clockt?p @*A0Agpt10_fck~ti,composite-clockt@Agpt11_gate_fck~ti,composite-gate-clockt p *B0Bgpt11_mux_fck~ti,composite-mux-clockt?p @*C0Cgpt11_fck~ti,composite-clocktBCcore_96m_fck~fixed-factor-clocktD*0mmchs2_fck~ti,wait-gate-clocktp *0mmchs1_fck~ti,wait-gate-clocktp *0i2c3_fck~ti,wait-gate-clocktp *0i2c2_fck~ti,wait-gate-clocktp *0i2c1_fck~ti,wait-gate-clocktp *0mcbsp5_gate_fck~ti,composite-gate-clockt p *0mcbsp1_gate_fck~ti,composite-gate-clockt p *0core_48m_fck~fixed-factor-clockt/*E0Emcspi4_fck~ti,wait-gate-clocktEp *0mcspi3_fck~ti,wait-gate-clocktEp *0mcspi2_fck~ti,wait-gate-clocktEp *0mcspi1_fck~ti,wait-gate-clocktEp *0uart2_fck~ti,wait-gate-clocktEp *0uart1_fck~ti,wait-gate-clocktEp  *0core_12m_fck~fixed-factor-clocktF*G0Ghdq_fck~ti,wait-gate-clocktGp *0core_l3_ick~fixed-factor-clockt=*H0Hsdrc_ick~ti,wait-gate-clocktHp *0gpmc_fck~fixed-factor-clocktHcore_l4_ick~fixed-factor-clockt>*I0Immchs2_ick~ti,omap3-interface-clocktIp *0mmchs1_ick~ti,omap3-interface-clocktIp *0hdq_ick~ti,omap3-interface-clocktIp *0mcspi4_ick~ti,omap3-interface-clocktIp *0mcspi3_ick~ti,omap3-interface-clocktIp *0mcspi2_ick~ti,omap3-interface-clocktIp *0mcspi1_ick~ti,omap3-interface-clocktIp *0i2c3_ick~ti,omap3-interface-clocktIp *0i2c2_ick~ti,omap3-interface-clocktIp *0i2c1_ick~ti,omap3-interface-clocktIp *0uart2_ick~ti,omap3-interface-clocktIp *0uart1_ick~ti,omap3-interface-clocktIp  *0gpt11_ick~ti,omap3-interface-clocktIp  *0gpt10_ick~ti,omap3-interface-clocktIp  *0mcbsp5_ick~ti,omap3-interface-clocktIp  *0mcbsp1_ick~ti,omap3-interface-clocktIp  *0omapctrl_ick~ti,omap3-interface-clocktIp *0dss_tv_fck~ti,gate-clockt7p*0dss_96m_fck~ti,gate-clocktDp*0dss2_alwon_fck~ti,gate-clocktp*0dummy_ck~ fixed-clockgpt1_gate_fck~ti,composite-gate-clocktp *J0Jgpt1_mux_fck~ti,composite-mux-clockt?p @*K0Kgpt1_fck~ti,composite-clocktJKaes2_ick~ti,omap3-interface-clocktIp *0wkup_32k_fck~fixed-factor-clockt?*L0Lgpio1_dbck~ti,gate-clocktLp *0sha12_ick~ti,omap3-interface-clocktIp *0wdt2_fck~ti,wait-gate-clocktLp *0wdt2_ick~ti,omap3-interface-clocktMp *0wdt1_ick~ti,omap3-interface-clocktMp *0gpio1_ick~ti,omap3-interface-clocktMp *0omap_32ksync_ick~ti,omap3-interface-clocktMp *0gpt12_ick~ti,omap3-interface-clocktMp *0gpt1_ick~ti,omap3-interface-clocktMp *0per_96m_fck~fixed-factor-clockt(* 0 per_48m_fck~fixed-factor-clockt/*N0Nuart3_fck~ti,wait-gate-clocktNp *0gpt2_gate_fck~ti,composite-gate-clocktp*O0Ogpt2_mux_fck~ti,composite-mux-clockt?p@*P0Pgpt2_fck~ti,composite-clocktOPgpt3_gate_fck~ti,composite-gate-clocktp*Q0Qgpt3_mux_fck~ti,composite-mux-clockt?p@*R0Rgpt3_fck~ti,composite-clocktQRgpt4_gate_fck~ti,composite-gate-clocktp*S0Sgpt4_mux_fck~ti,composite-mux-clockt?p@*T0Tgpt4_fck~ti,composite-clocktSTgpt5_gate_fck~ti,composite-gate-clocktp*U0Ugpt5_mux_fck~ti,composite-mux-clockt?p@*V0Vgpt5_fck~ti,composite-clocktUVgpt6_gate_fck~ti,composite-gate-clocktp*W0Wgpt6_mux_fck~ti,composite-mux-clockt?p@*X0Xgpt6_fck~ti,composite-clocktWXgpt7_gate_fck~ti,composite-gate-clocktp*Y0Ygpt7_mux_fck~ti,composite-mux-clockt?p@*Z0Zgpt7_fck~ti,composite-clocktYZgpt8_gate_fck~ti,composite-gate-clockt p*[0[gpt8_mux_fck~ti,composite-mux-clockt?p@*\0\gpt8_fck~ti,composite-clockt[\gpt9_gate_fck~ti,composite-gate-clockt p*]0]gpt9_mux_fck~ti,composite-mux-clockt?p@*^0^gpt9_fck~ti,composite-clockt]^per_32k_alwon_fck~fixed-factor-clockt?*_0_gpio6_dbck~ti,gate-clockt_p*0gpio5_dbck~ti,gate-clockt_p*0gpio4_dbck~ti,gate-clockt_p*0gpio3_dbck~ti,gate-clockt_p*0gpio2_dbck~ti,gate-clockt_p *0wdt3_fck~ti,wait-gate-clockt_p *0per_l4_ick~fixed-factor-clockt>*`0`gpio6_ick~ti,omap3-interface-clockt`p*0gpio5_ick~ti,omap3-interface-clockt`p*0gpio4_ick~ti,omap3-interface-clockt`p*0gpio3_ick~ti,omap3-interface-clockt`p*0gpio2_ick~ti,omap3-interface-clockt`p *0wdt3_ick~ti,omap3-interface-clockt`p *0uart3_ick~ti,omap3-interface-clockt`p *0uart4_ick~ti,omap3-interface-clockt`p*0gpt9_ick~ti,omap3-interface-clockt`p *0gpt8_ick~ti,omap3-interface-clockt`p *0gpt7_ick~ti,omap3-interface-clockt`p*0gpt6_ick~ti,omap3-interface-clockt`p*0gpt5_ick~ti,omap3-interface-clockt`p*0gpt4_ick~ti,omap3-interface-clockt`p*0gpt3_ick~ti,omap3-interface-clockt`p*0gpt2_ick~ti,omap3-interface-clockt`p*0mcbsp2_ick~ti,omap3-interface-clockt`p*0mcbsp3_ick~ti,omap3-interface-clockt`p*0mcbsp4_ick~ti,omap3-interface-clockt`p*0mcbsp2_gate_fck~ti,composite-gate-clocktp* 0 mcbsp3_gate_fck~ti,composite-gate-clocktp* 0 mcbsp4_gate_fck~ti,composite-gate-clocktp*0emu_src_mux_ck~ ti,mux-clocktabcp@*d0demu_src_ck~ti,clkdm-gate-clocktd*e0epclk_fck~ti,divider-clocktep@pclkx2_fck~ti,divider-clocktep@atclk_fck~ti,divider-clocktep@traceclk_src_fck~ ti,mux-clocktabcp@*f0ftraceclk_fck~ti,divider-clocktf p@secure_32k_fck~ fixed-clock*g0ggpt12_fck~fixed-factor-clocktgwdt1_fck~fixed-factor-clocktgsecurity_l4_ick2~fixed-factor-clockt>*h0haes1_ick~ti,omap3-interface-clockthp rng_ick~ti,omap3-interface-clockthp sha11_ick~ti,omap3-interface-clockthp des1_ick~ti,omap3-interface-clockthp cam_mclk~ti,gate-clocktipcam_ick~!ti,omap3-no-wait-interface-clockt>p*0csi2_96m_fck~ti,gate-clocktp*0security_l3_ick~fixed-factor-clockt=*j0jpka_ick~ti,omap3-interface-clocktjp icr_ick~ti,omap3-interface-clocktIp des2_ick~ti,omap3-interface-clocktIp mspro_ick~ti,omap3-interface-clocktIp mailboxes_ick~ti,omap3-interface-clocktIp ssi_l4_ick~fixed-factor-clockt>*q0qsr1_fck~ti,wait-gate-clocktp sr2_fck~ti,wait-gate-clocktp sr_l4_ick~fixed-factor-clockt>dpll2_fck~ti,divider-clockt%p@*k0kdpll2_ck~ti,omap3-dpll-clocktkp$@4HZb*l0ldpll2_m2_ck~ti,divider-clocktlpD*m0miva2_ck~ti,wait-gate-clocktmp*0modem_fck~ti,omap3-interface-clocktp *0sad2d_ick~ti,omap3-interface-clockt=p *0mad2d_ick~ti,omap3-interface-clockt=p *0mspro_fck~ti,wait-gate-clocktp ssi_ssr_gate_fck_3430es2~ ti,composite-no-wait-gate-clocktp *n0nssi_ssr_div_fck_3430es2~ti,composite-divider-clocktp @$v*o0ossi_ssr_fck_3430es2~ti,composite-clocktno*p0pssi_sst_fck_3430es2~fixed-factor-clocktp*0hsotgusb_ick_3430es2~"ti,omap3-hsotgusb-interface-clocktHp *0ssi_ick_3430es2~ti,omap3-ssi-interface-clocktqp *0usim_gate_fck~ti,composite-gate-clocktD p *|0|sys_d2_ck~fixed-factor-clockt*s0somap_96m_d2_fck~fixed-factor-clocktD*t0tomap_96m_d4_fck~fixed-factor-clocktD*u0uomap_96m_d8_fck~fixed-factor-clocktD*v0vomap_96m_d10_fck~fixed-factor-clocktD *w0wdpll5_m2_d4_ck~fixed-factor-clocktr*x0xdpll5_m2_d8_ck~fixed-factor-clocktr*y0ydpll5_m2_d16_ck~fixed-factor-clocktr*z0zdpll5_m2_d20_ck~fixed-factor-clocktr*{0{usim_mux_fck~ti,composite-mux-clock(tstuvwxyz{p @*}0}usim_fck~ti,composite-clockt|}usim_ick~ti,omap3-interface-clocktMp  *0dpll5_ck~ti,omap3-dpll-clocktp  $ L 4HZ*~0~dpll5_m2_ck~ti,divider-clockt~p P*r0rsgx_gate_fck~ti,composite-gate-clockt%p *0core_d3_ck~fixed-factor-clockt%*0core_d4_ck~fixed-factor-clockt%*0core_d6_ck~fixed-factor-clockt%*0omap_192m_alwon_fck~fixed-factor-clockt!*0core_d2_ck~fixed-factor-clockt%*0sgx_mux_fck~ti,composite-mux-clock t)p @*0sgx_fck~ti,composite-clocktsgx_ick~ti,wait-gate-clockt=p *0cpefuse_fck~ti,gate-clocktp *0ts_fck~ti,gate-clockt?p *0usbtll_fck~ti,wait-gate-clocktrp *0usbtll_ick~ti,omap3-interface-clocktIp *0mmchs3_ick~ti,omap3-interface-clocktIp *0mmchs3_fck~ti,wait-gate-clocktp *0dss1_alwon_fck_3430es2~ti,dss-gate-clocktp*0dss_ick_3430es2~ti,omap3-dss-interface-clockt>p*0usbhost_120m_fck~ti,gate-clocktrp*0usbhost_48m_fck~ti,dss-gate-clockt/p*0usbhost_ick~ti,omap3-dss-interface-clockt>p*0clockdomainscore_l3_clkdmti,clockdomaintdpll3_clkdmti,clockdomaintdpll1_clkdmti,clockdomaintper_clkdmti,clockdomainhtemu_clkdmti,clockdomaintedpll4_clkdmti,clockdomaintwkup_clkdmti,clockdomain$tdss_clkdmti,clockdomaintcore_l4_clkdmti,clockdomaintcam_clkdmti,clockdomaintiva2_clkdmti,clockdomaintdpll2_clkdmti,clockdomaintld2d_clkdmti,clockdomain tdpll5_clkdmti,clockdomaint~sgx_clkdmti,clockdomaintusbhost_clkdmti,clockdomain tcounter@48320000ti,omap-counter32kpH2  counter_32kinterrupt-controller@48200000ti,omap3-intcpH *0dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmapH`  `*0gpio@48310000ti,omap3-gpiopH1gpio1gpio@49050000ti,omap3-gpiopIgpio2gpio@49052000ti,omap3-gpiopI gpio3gpio@49054000ti,omap3-gpiopI@ gpio4gpio@49056000ti,omap3-gpiopI`!gpio5gpio@49058000ti,omap3-gpiopI"gpio6serial@4806a000ti,omap3-uartpH H12txrxuart1lserial@4806c000ti,omap3-uartpHI34txrxuart2lserial@49020000ti,omap3-uartpIJ56txrxuart3li2c@48070000 ti,omap3-i2cpH8txrxi2c1i2c@48072000 ti,omap3-i2cpH 9txrxi2c2i2c@48060000 ti,omap3-i2cpH=txrxi2c3mailbox@48094000ti,omap3-mailboxmailboxpH @dsp  $spi@48098000ti,omap2-mcspipH Amcspi1/@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspipH Bmcspi2/ +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspipH [mcspi3/ tx0rx0tx1rx1spi@480ba000ti,omap2-mcspipH 0mcspi4/FGtx0rx01w@480b2000 ti,omap3-1wpH :hdq1wmmc@4809c000ti,omap3-hsmmcpH Smmc1==>txrxJmmc@480b4000ti,omap3-hsmmcpH @Vmmc2/0txrxmmc@480ad000ti,omap3-hsmmcpH ^mmc3MNtxrxmmu@480bd400Wti,omap2-iommupH mmu_ispd*0mmu@5d000000Wti,omap2-iommup]mmu_iva disabledwdt@48314000 ti,omap3-wdtpH1@ wd_timer2mcbsp@48074000ti,omap3-mcbsppH@tmpu ;< ~commontxrxmcbsp1 txrx disabledmcbsp@49022000ti,omap3-mcbsppI I tmpusidetone>?~commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx disabledmcbsp@49024000ti,omap3-mcbsppI@I tmpusidetoneYZ~commontxrxsidetonemcbsp3mcbsp3_sidetonetxrx disabledmcbsp@49026000ti,omap3-mcbsppI`tmpu 67 ~commontxrxmcbsp4txrx disabledmcbsp@48096000ti,omap3-mcbsppH `tmpu QR ~commontxrxmcbsp5txrx disabledsham@480c3000ti,omap3-shamshampH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corepH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivapH timer@48318000ti,omap3430-timerpH1%timer1timer@49032000ti,omap3430-timerpI &timer2timer@49034000ti,omap3430-timerpI@'timer3timer@49036000ti,omap3430-timerpI`(timer4timer@49038000ti,omap3430-timerpI)timer5timer@4903a000ti,omap3430-timerpI*timer6timer@4903c000ti,omap3430-timerpI+timer7timer@4903e000ti,omap3430-timerpI,timer8timer@49040000ti,omap3430-timerpI-timer9timer@48086000ti,omap3430-timerpH`.timer10timer@48088000ti,omap3430-timerpH/timer11timer@48304000ti,omap3430-timerpH0@_timer12usbhstll@48062000 ti,usbhs-tllpH N usb_tll_hsusbhshost@48064000ti,usbhs-hostpH@ usb_host_hsohci@48064400ti,ohci-omap3pHD&Lehci@48064800 ti,ehci-omappHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcpnrxtxusb_otg_hs@480ab000ti,omap3-musbpH \]~mcdma usb_otg_hs dss@48050000 ti,omap3-dsspH disabled dss_coret{fckdispc@48050400ti,omap3-dispcpH dss_dispct{fckencoder@4804fc00 ti,omap3-dsipHH@H tprotophypll disabled dss_dsi1t {fcksys_clkencoder@48050800ti,omap3-rfbipH disabled dss_rfbit{fckickencoder@48050c00ti,omap3-vencpH  disabled dss_venct{fckssi-controller@48058000 ti,omap3-ssissiokpHHtsysgddG~gdd_mpu tp {ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portpHHttxrx&CDssi-port@4805b000ti,omap3-ssi-portpHHttxrx&EFpinmux@480025d8 ti,omap3-padconfpinctrl-singlepH%$ isp@480bc000 ti,omap3-isppH H |8~ports #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsstatusranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extended#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supply#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsiommusti,phy-type