8 (7radxa,rockpi-n8vamrs,rk3288-vmarc-somrockchip,rk3288&7Radxa ROCK Pi N8aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rVcpu@501cpuarm,cortex-a12'@5<rVcpu@502cpuarm,cortex-a12'@5<rVcpu@503cpuarm,cortex-a12'@5<rVcpu-opp-tableoperating-points-v2^Vopp-126000000ip opp-216000000i p opp-312000000ip opp-408000000iQp opp-600000000i#Fp opp-696000000i)|p~opp-816000000i0,pB@opp-1008000000i<popp-1200000000iGpopp-1416000000iTfrpOopp-1512000000iZJp opp-1608000000i_"ppbus simple-bus~dma-controller@ff250000arm,pl330arm,primecell%@5 apb_pclkVdma-controller@ff600000arm,pl330arm,primecell`@5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@5 apb_pclkV\reserved-memory~dma-unusable@fe000000oscillator fixed-clockn6xin24mV timerarm,armv7-timer0   n6)timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem@ mmc@ff0c0000rockchip,rk3288-dw-mshcFр 5Drvbiuciuciu-driveciu-sampleT  @_resetokayku default mmc@ff0d0000rockchip,rk3288-dw-mshcFр 5Eswbiuciuciu-driveciu-sampleT ! @_resetokaykdefault mmc@ff0e0000rockchip,rk3288-dw-mshcFр 5Ftxbiuciuciu-driveciu-sampleT "@_reset disabledmmc@ff0f0000rockchip,rk3288-dw-mshcFр 5Guybiuciuciu-driveciu-sampleT #@_resetokaykudefaultsaradc@ff100000rockchip,saradc $5I[saradcapb_pclkW _saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk0  5txrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk0 5txrx -default !"# disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclk05txrx .default$%&' disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault(okayrtc@51haoyu,hym8563Q&)hym8563default*Vi2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault+ disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault, disabledi2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault-okayVrserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7?I5MUbaudclkapb_pclk05txrxdefault./okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8?I5NVbaudclkapb_pclk05txrxdefault0 disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9?I5OWbaudclkapb_pclkdefault1okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :?I5PXbaudclkapb_pclk05txrxdefault2 disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;?I5QYbaudclkapb_pclk0  5txrxdefault3 disabledthermal-zonesreserve_thermalVlz4cpu_thermalVdlz4tripscpu_alert0ppassiveV5cpu_alert1$passiveV6cpu_crit_ criticalcooling-mapsmap050map160gpu_thermalVdlz4tripsgpu_alert0ppassiveV7gpu_crit_ criticalcooling-mapsmap07 8tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk _tsadc-apbinitdefaultsleep9:9;s disabledV4ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq;85fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB _stmmacethokay<*input7rgmiidefault=@ V'Pk(t} >usb@ff500000 generic-ehciP 5?usbokayusb@ff520000 generic-ohciR )5?usbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghost@ usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otgotg@@ A usb2-phyokayusb@ff5c0000 generic-ehci\ 5 disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5LdefaultBokaypmic@1brockchip,rk808&CdefaultDE'rk808-clkout1rk808-clkout25FAFMFYFeFqF}FFregulatorsDCDC_REG1vdd_arm q\regulator-state-mem.DCDC_REG2vdd_gpu PGpregulator-state-mem.DCDC_REG3vcc_ddrregulator-state-mem\DCDC_REG4vcc_io2Z2ZVregulator-state-mem\t2ZLDO_REG1vcc_tp2Z2Zregulator-state-mem.LDO_REG2 vcca_codec2Z2Zregulator-state-mem\t2ZLDO_REG3vdd_10B@B@regulator-state-mem\tB@LDO_REG4vcc_wlw@w@V[regulator-state-mem\LDO_REG5 vccio_sdw@2ZV regulator-state-mem\t2ZLDO_REG6 vdd10_lcdB@B@regulator-state-mem.LDO_REG7vcc_18w@w@VZregulator-state-mem\tw@LDO_REG8 vcc18_lcdw@w@regulator-state-mem.SWITCH_REG1vcc_sdregulator-state-mem.SWITCH_REG2vcc_lcdregulator-state-mem.i2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultG disabledpwm@ff680000rockchip,rk3288-pwmhdefaultH5_pwmokaypwm@ff680010rockchip,rk3288-pwmhdefaultI5_pwm disabledpwm@ff680020rockchip,rk3288-pwmh defaultJ5_pwmokaypwm@ff680030rockchip,rk3288-pwmh0defaultK5_pwm disabledsram@ff700000 mmio-sramp~psmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsVpower-controller!rockchip,rk3288-power-controller}h V_pd_vio@9 5chgfdehilkj$LMNOPQRSTpd_hevc@11 5opUVpd_video@12 5Wpd_gpu@13 5XYreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv;H}jk$#gׄeрxhрxhVsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwV;edp-phyrockchip,rk3288-dp-phy5h24m disabledVoio-domains"rockchip,rk3288-io-voltage-domainokay *8ZHV d[usbphyrockchip,rk3288-usb-phyokayusb-phy@320 5]phyclk _phy-resetVAusb-phy@33445^phyclk _phy-resetV?usb-phy@348H5_phyclk _phy-resetV@watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p O disabledsound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifp5T mclkhclk0\5tx 6default]; disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2sp 55Ri2s_clki2s_hclk0\\5txrxdefault^ disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk _crypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu5 aclkiface disablediommu@ff914000rockchip,iommu @P isp_mmu5 aclkiface disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclk_ ilm _coreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop_ def _axiahbdclk`okayportV endpoint@0aVtendpoint@1bVpendpoint@2cVjendpoint@3dVmiommu@ff930300rockchip,iommu  vopb_mmu5 aclkiface_ okayV`vop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop_  _axiahbdclkeokayportV endpoint@0fVuendpoint@1gVqendpoint@2hVkendpoint@3iVniommu@ff940300rockchip,iommu  vopl_mmu5 aclkiface_ okayVemipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclk_ ; disabledportsportendpoint@0jVcendpoint@1kVhlvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcl_ ; disabledportsport@0endpoint@0mVdendpoint@1nVidp@ff970000rockchip,rk3288-dp@ b5icdppclkodpo_dp; disabledportsport@0endpoint@0pVbendpoint@1qVghdmi@ff980000rockchip,rk3288-dw-hdmiIp; g5hmniahbisfrcec_ okayrdefaultsportsportendpoint@0tVaendpoint@1uVfvideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu5 aclkhclkv_ iommu@ff9a0800rockchip,iommu vpu_mmu5 aclkiface_ Vviommu@ff9c0440rockchip,iommu @@@ o hevc_mmu5 aclkiface disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu5w_  disabledV8gpu-opp-tableoperating-points-v2Vwopp-100000000ip~opp-200000000i p~opp-300000000ipB@opp-400000000iׄpopp-600000000i#Fpqos@ffaa0000syscon VXqos@ffaa0080syscon VYqos@ffad0000syscon VMqos@ffad0100syscon VNqos@ffad0180syscon VOqos@ffad0400syscon VPqos@ffad0480syscon VQqos@ffad0500syscon VLqos@ffad0800syscon VRqos@ffad0880syscon VSqos@ffad0900syscon VTqos@ffae0000syscon VWqos@ffaf0000syscon VUqos@ffaf0080syscon VVefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400$@ @ `   Vpinctrlrockchip,rk3288-pinctrl;~gpio0@ff750000rockchip,gpio-banku Q5@5E$VCgpio1@ff780000rockchip,gpio-bankx R5A5E$gpio2@ff790000rockchip,gpio-banky S5B5E$gpio3@ff7a0000rockchip,gpio-bankz T5C5E$gpio4@ff7b0000rockchip,gpio-bank{ U5D5E$V>gpio5@ff7c0000rockchip,gpio-bank| V5E5E$V)gpio6@ff7d0000rockchip,gpio-bank} W5F5E$gpio7@ff7e0000rockchip,gpio-bank~ X5G5E$gpio8@ff7f0000rockchip,gpio-bank Y5H5E$hdmihdmi-cec-c0QxVshdmi-cec-c7Qxhdmi-ddc Qxxhdmi-ddc-unwedge Qyxpcfg-output-low_Vypcfg-pull-upjVzpcfg-pull-downwV{pcfg-pull-noneVxpcfg-pull-none-12ma V~sleepglobal-pwroffQxVEddrio-pwroffQxddr0-retentionQzddr1-retentionQzedpedp-hpdQ {i2c0i2c0-xfer QxxVBi2c1i2c1-xfer QxxV(i2c2i2c2-xfer Q x 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~~xxV=rmii-pinsQxxxxxxxxxxspdifspdif-txQ xV]hym8563hym8563-intQzV*pcfg-pull-none-drv-8maV|pcfg-pull-up-drv-8majV}pmicpmic-intQzVDsdio-pwrseqwifi-enable-hQxVvbus_hostusb1-en-ocQzVvbus_typecusb0-en-ocQ zVexternal-gmac-clock fixed-clocksY@ clkin_gmacV<sdio-pwrseqmmc-pwrseq-simple5 ext_clockdefault >Vvcc12v-dcin-regulatorregulator-fixed vcc12v_dcinVvcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@VFvbus-hostregulator-fixeddefault vbus_hostF Cvbus-typecregulator-fixeddefault vbus_typecF C vccio-flash-regulatorregulator-fixed vccio_flashw@w@V #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvqmmc-supplypinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104vmmc-supply#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-tempinterrupt-namesassigned-clock-parentsclock_in_outphy-modesnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayassigned-clocksphy-supplysnps,reset-gpiophysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-off-in-suspendregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplyflash0-supplygpio1830-supplygpio30-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthreset-gpiosvin-supplyenable-active-high