8d( ,nvidia,beavernvidia,tegra30 +'7NVIDIA Tegra30 Beaver evaluation boardemc-dvfs-opp-tableoperating-points-v2=opp@12750000,950 E~~pSŒZopp@12750000,1000 EB@B@pSŒZopp@12750000,1250 EpSŒZopp@25500000,950 E~~pS`Zopp@25500000,1000 EB@B@pS`Zopp@25500000,1250 EpS`Zopp@27000000,950 E~~pSZopp@27000000,1000 EB@B@pSZopp@27000000,1250 EpSZopp@51000000,950 E~~pS 2Zopp@51000000,1000 EB@B@pS 2Zopp@51000000,1250 EpS 2Zopp@54000000,950 E~~pS7Zopp@54000000,1000 EB@B@pS7Zopp@54000000,1250 EpS7Zopp@102000000,950 E~~pSeZopp@102000000,1000 EB@B@pSeZopp@102000000,1250 EpSeZopp@108000000,1000 EB@B@pSoZopp@108000000,1250 EpSoZopp@204000000,1000 EB@B@pS (Zkopp@204000000,1250 EpS (Zkopp@333500000,1000 EB@B@pS`Zopp@333500000,1200 EOOpS`Zopp@333500000,1250 EpS`Zopp@375000000,1000 EB@B@pSZ Zopp@375000000,1200 EOOpSZ Zopp@375000000,1250 EpSZ Zopp@400000000,1000 EB@B@pSׄZopp@400000000,1200 EOOpSׄZopp@400000000,1250 EpSׄZopp@416000000,1200 EOOpS˨Zopp@416000000,1250 EpS˨Zopp@450000000,1200 EOOpStZopp@450000000,1250 EpStZopp@533000000,1200 EOOpS@Zopp@533000000,1250 EpS@Zopp@625000000,1200 EOOpS%@@Zopp@625000000,1250 EpS%@@Zopp@667000000,1200 EOOpS'Zopp@750000000,1300 E  pS,Zopp@800000000,1300 E  pS/Zopp@900000000,1350 EpppS5Zemc-bandwidth-opp-tableoperating-points-v2= opp@12750000SŒZwpopp@25500000S`Zwopp@27000000SZwKopp@51000000S 2Zw9opp@54000000S7Zwopp@102000000SeZw sopp@108000000SoZw /opp@204000000S (Zwkopp@333500000S`Zw(opp@375000000SZ Zw-opp@400000000SׄZw0opp@416000000S˨Zw2opp@450000000StZw6opp@533000000S@ZwA@opp@625000000S%@@ZwLK@opp@667000000S'ZwQkopp@750000000S,Zw[opp@800000000S/Zwaopp@900000000S5Zwmmemory@80000000memorypcie@3000nvidia,tegra30-pciepci08 padsaficsbc intrmsi b+@@ B(( FHpexafipll_ecmlFHJpexafipcie_x#okay*+;<L`qpci@1,0pci#okay+pci@2,0pci #disabled+pci@3,0pci@#okay+sram@40000000 mmio-sram@+ @sram@400=host1x@50000000nvidia,tegra30-host1xP@ACsyncpthost1xhost1xhost1x + TTmpe@54040000nvidia,tegra30-mpeT D<<mpevi@54080000nvidia,tegra30-viT Eviepp@540c0000nvidia,tegra30-eppT  Feppisp@54100000nvidia,tegra30-ispT Gispgr2d@54140000nvidia,tegra30-gr2dT H2dgr3d@54180000nvidia,tegra30-gr3dTb3d3d2b3d3d2  dc@54200000nvidia,tegra30-dcT  I dcparentdc<#winawinbwinb-vfilterwinccursorrgb #disableddc@54240000nvidia,tegra30-dcT$ J dcparentdc<#winawinbwinb-vfilterwinccursorrgb #disabledhdmi@54280000nvidia,tegra30-hdmiT( K3 hdmiparent3hdmi#okay U   o tvo@542c0000nvidia,tegra30-tvoT, L #disableddsi@54300000nvidia,tegra30-dsiT00 dsiparent0dsi #disableddsi@54400000nvidia,tegra30-dsiT@R dsiparentTdsi #disabledtimer@50040600arm,cortex-a9-twd-timerP    interrupt-controller@50041000arm,cortex-a9-gicPP- =cache-controller@50043000arm,pl310-cacheP0 B Scqinterrupt-controller@60004000nvidia,tegra30-ictlr(`@`AP`BP`CP`DP- =timer@60005000*nvidia,tegra30-timernvidia,tegra20-timer`PH)*yzclock@60006000nvidia,tegra30-car``}=flow-controller@60007000nvidia,tegra30-flowctrl`pdma@6000a000,nvidia,tegra30-apbdmanvidia,tegra20-apbdma`hijklmnopqrstuvw""dma=ahb@6000c000nvidia,tegra30-ahb`Pactmon@6000c800nvidia,tegra30-actmon` -w9 actmonemcwactmon  ' cpu-readgpio@6000d000nvidia,tegra30-gpio`` !"#7WY}-= vde@6001a000&nvidia,tegra30-vdenvidia,tegra20-vdeH`````````*sxebsevmbeppemcetfeppbvdmaframeid$   sync-tokenbsevsxe=vdemc=apbmisc@70000800.nvidia,tegra30-apbmiscnvidia,tegra20-apbmiscpdppinmux@70000868nvidia,tegra30-pinmuxphp0defaultpinmux=clk_32k_out_pa0clk_32k_out_pa0blink 'uart3_cts_n_pa1uart3_cts_n_pa1uartc 'dap2_fs_pa2 dap2_fs_pa2i2s1 'dap2_sclk_pa3dap2_sclk_pa3i2s1 'dap2_din_pa4 dap2_din_pa4i2s1 'dap2_dout_pa5dap2_dout_pa5i2s1 'sdmmc3_clk_pa6sdmmc3_clk_pa6sdmmc3 'sdmmc3_cmd_pa7sdmmc3_cmd_pa7sdmmc3 'gmi_a17_pb0 gmi_a17_pb0spi4 'gmi_a18_pb1 gmi_a18_pb1spi4 'lcd_pwr0_pb2 lcd_pwr0_pb2 displaya 'lcd_pclk_pb3 lcd_pclk_pb3 displaya 'sdmmc3_dat3_pb4sdmmc3_dat3_pb4sdmmc3 'sdmmc3_dat2_pb5sdmmc3_dat2_pb5sdmmc3 'sdmmc3_dat1_pb6sdmmc3_dat1_pb6sdmmc3 'sdmmc3_dat0_pb7sdmmc3_dat0_pb7sdmmc3 'uart3_rts_n_pc0uart3_rts_n_pc0uartc 'lcd_pwr1_pc1 lcd_pwr1_pc1 displaya 'uart2_txd_pc2uart2_txd_pc2uartb 'uart2_rxd_pc3uart2_rxd_pc3uartb 'gen1_i2c_scl_pc4gen1_i2c_scl_pc4i2c1 ';gen1_i2c_sda_pc5gen1_i2c_sda_pc5i2c1 ';lcd_pwr2_pc6 lcd_pwr2_pc6 displaya 'gmi_wp_n_pc7 gmi_wp_n_pc7gmi 'sdmmc3_dat5_pd0sdmmc3_dat5_pd0sdmmc3 'sdmmc3_dat4_pd1sdmmc3_dat4_pd1sdmmc3 'lcd_dc1_pd2 lcd_dc1_pd2 displaya 'sdmmc3_dat6_pd3sdmmc3_dat6_pd3spdif 'sdmmc3_dat7_pd4sdmmc3_dat7_pd4spdif 'vi_d1_pd5 vi_d1_pd5sdmmc2 'vi_vsync_pd6 vi_vsync_pd6ddr 'vi_hsync_pd7 vi_hsync_pd7ddr 'lcd_d0_pe0 lcd_d0_pe0 displaya 'lcd_d1_pe1 lcd_d1_pe1 displaya 'lcd_d2_pe2 lcd_d2_pe2 displaya 'lcd_d3_pe3 lcd_d3_pe3 displaya 'lcd_d4_pe4 lcd_d4_pe4 displaya 'lcd_d5_pe5 lcd_d5_pe5 displaya 'lcd_d6_pe6 lcd_d6_pe6 displaya 'lcd_d7_pe7 lcd_d7_pe7 displaya 'lcd_d8_pf0 lcd_d8_pf0 displaya 'lcd_d9_pf1 lcd_d9_pf1 displaya 'lcd_d10_pf2 lcd_d10_pf2 displaya 'lcd_d11_pf3 lcd_d11_pf3 displaya 'lcd_d12_pf4 lcd_d12_pf4 displaya 'lcd_d13_pf5 lcd_d13_pf5 displaya 'lcd_d14_pf6 lcd_d14_pf6 displaya 'lcd_d15_pf7 lcd_d15_pf7 displaya 'gmi_ad0_pg0 gmi_ad0_pg0nand 'gmi_ad1_pg1 gmi_ad1_pg1nand 'gmi_ad2_pg2 gmi_ad2_pg2nand 'gmi_ad3_pg3 gmi_ad3_pg3nand 'gmi_ad4_pg4 gmi_ad4_pg4nand 'gmi_ad5_pg5 gmi_ad5_pg5nand 'gmi_ad6_pg6 gmi_ad6_pg6nand 'gmi_ad7_pg7 gmi_ad7_pg7nand 'gmi_ad8_ph0 gmi_ad8_ph0pwm0 'gmi_ad9_ph1 gmi_ad9_ph1pwm1 'gmi_ad10_ph2 gmi_ad10_ph2nand 'gmi_ad11_ph3 gmi_ad11_ph3nand 'gmi_ad12_ph4 gmi_ad12_ph4nand 'gmi_ad13_ph5 gmi_ad13_ph5nand 'gmi_ad14_ph6 gmi_ad14_ph6nand 'gmi_wr_n_pi0 gmi_wr_n_pi0nand 'gmi_oe_n_pi1 gmi_oe_n_pi1nand 'gmi_dqs_pi2 gmi_dqs_pi2nand 'gmi_iordy_pi5gmi_iordy_pi5rsvd1 'gmi_cs7_n_pi6gmi_cs7_n_pi6nand 'gmi_wait_pi7 gmi_wait_pi7nand 'lcd_de_pj1 lcd_de_pj1 displaya 'lcd_hsync_pj3lcd_hsync_pj3 displaya 'lcd_vsync_pj4lcd_vsync_pj4 displaya 'uart2_cts_n_pj5uart2_cts_n_pj5uartb 'uart2_rts_n_pj6uart2_rts_n_pj6uartb 'gmi_a16_pj7 gmi_a16_pj7spi4 'gmi_adv_n_pk0gmi_adv_n_pk0nand 'gmi_clk_pk1 gmi_clk_pk1nand 'gmi_cs2_n_pk3gmi_cs2_n_pk3rsvd1 'gmi_cs3_n_pk4gmi_cs3_n_pk4nand 'spdif_out_pk5spdif_out_pk5spdif 'spdif_in_pk6 spdif_in_pk6spdif 'gmi_a19_pk7 gmi_a19_pk7spi4 'vi_d2_pl0 vi_d2_pl0sdmmc2 'vi_d3_pl1 vi_d3_pl1sdmmc2 'vi_d4_pl2 vi_d4_pl2vi 'vi_d5_pl3 vi_d5_pl3sdmmc2 'vi_d6_pl4 vi_d6_pl4vi 'vi_d7_pl5 vi_d7_pl5sdmmc2 'vi_d8_pl6 vi_d8_pl6sdmmc2 'vi_d9_pl7 vi_d9_pl7sdmmc2 'lcd_d16_pm0 lcd_d16_pm0 displaya 'lcd_d17_pm1 lcd_d17_pm1 displaya 'lcd_d18_pm2 lcd_d18_pm2 displaya 'lcd_d19_pm3 lcd_d19_pm3 displaya 'lcd_d20_pm4 lcd_d20_pm4 displaya 'lcd_d21_pm5 lcd_d21_pm5 displaya 'lcd_d22_pm6 lcd_d22_pm6 displaya 'lcd_d23_pm7 lcd_d23_pm7 displaya 'dap1_fs_pn0 dap1_fs_pn0i2s0 'dap1_din_pn1 dap1_din_pn1i2s0 'dap1_dout_pn2dap1_dout_pn2i2s0 'dap1_sclk_pn3dap1_sclk_pn3i2s0 'lcd_cs0_n_pn4lcd_cs0_n_pn4 displaya 'lcd_sdout_pn5lcd_sdout_pn5 displaya 'lcd_dc0_pn6 lcd_dc0_pn6 displaya 'hdmi_int_pn7 hdmi_int_pn7hdmi 'ulpi_data7_po0ulpi_data7_po0uarta 'ulpi_data0_po1ulpi_data0_po1uarta 'ulpi_data1_po2ulpi_data1_po2uarta 'ulpi_data2_po3ulpi_data2_po3uarta 'ulpi_data3_po4ulpi_data3_po4uarta 'ulpi_data4_po5ulpi_data4_po5uarta 'ulpi_data5_po6ulpi_data5_po6uarta 'ulpi_data6_po7ulpi_data6_po7uarta 'dap3_fs_pp0 dap3_fs_pp0i2s2 'dap3_din_pp1 dap3_din_pp1i2s2 'dap3_dout_pp2dap3_dout_pp2i2s2 'dap3_sclk_pp3dap3_sclk_pp3i2s2 'dap4_fs_pp4 dap4_fs_pp4i2s3 'dap4_din_pp5 dap4_din_pp5i2s3 'dap4_dout_pp6dap4_dout_pp6i2s3 'dap4_sclk_pp7dap4_sclk_pp7i2s3 'kb_col0_pq0 kb_col0_pq0kbc 'kb_col1_pq1 kb_col1_pq1kbc 'kb_col2_pq2 kb_col2_pq2kbc 'kb_col3_pq3 kb_col3_pq3kbc 'kb_col4_pq4 kb_col4_pq4kbc 'kb_col5_pq5 kb_col5_pq5kbc 'kb_col6_pq6 kb_col6_pq6kbc 'kb_col7_pq7 kb_col7_pq7kbc 'kb_row0_pr0 kb_row0_pr0kbc 'kb_row1_pr1 kb_row1_pr1kbc 'kb_row2_pr2 kb_row2_pr2kbc 'kb_row3_pr3 kb_row3_pr3kbc 'kb_row4_pr4 kb_row4_pr4kbc 'kb_row5_pr5 kb_row5_pr5kbc 'kb_row6_pr6 kb_row6_pr6kbc 'kb_row7_pr7 kb_row7_pr7kbc 'kb_row8_ps0 kb_row8_ps0kbc 'kb_row9_ps1 kb_row9_ps1kbc 'kb_row10_ps2 kb_row10_ps2kbc 'kb_row11_ps3 kb_row11_ps3kbc 'kb_row12_ps4 kb_row12_ps4kbc 'kb_row13_ps5 kb_row13_ps5kbc 'kb_row14_ps6 kb_row14_ps6kbc 'kb_row15_ps7 kb_row15_ps7kbc 'vi_pclk_pt0 vi_pclk_pt0rsvd1 'vi_mclk_pt1 vi_mclk_pt1vi 'vi_d10_pt2 vi_d10_pt2ddr 'vi_d11_pt3 vi_d11_pt3ddr 'vi_d0_pt4 vi_d0_pt4ddr 'gen2_i2c_scl_pt5gen2_i2c_scl_pt5i2c2 ';gen2_i2c_sda_pt6gen2_i2c_sda_pt6i2c2 ';sdmmc4_cmd_pt7sdmmc4_cmd_pt7sdmmc4 'pu0pu0owr 'pu1pu1rsvd1 'pu2pu2rsvd1 'pu3pu3pwm0 'pu4pu4pwm1 'pu5pu5pwm2 'pu6pu6pwm3 'jtag_rtck_pu7jtag_rtck_pu7rtck 'pv0pv0rsvd1 'pv2pv2owr 'pv3pv3 clk_12m_out 'ddc_scl_pv4 ddc_scl_pv4i2c4 'ddc_sda_pv5 ddc_sda_pv5i2c4 'crt_hsync_pv6crt_hsync_pv6crt 'crt_vsync_pv7crt_vsync_pv7crt 'lcd_cs1_n_pw0lcd_cs1_n_pw0 displaya 'lcd_m1_pw1 lcd_m1_pw1 displaya 'spi2_cs1_n_pw2spi2_cs1_n_pw2spi2 'clk1_out_pw4 clk1_out_pw4 extperiph1 'clk2_out_pw5 clk2_out_pw5 extperiph2 'uart3_txd_pw6uart3_txd_pw6uartc 'uart3_rxd_pw7uart3_rxd_pw7uartc 'spi2_sck_px2 spi2_sck_px2gmi 'spi1_mosi_px4spi1_mosi_px4spi1 'spi1_sck_px5 spi1_sck_px5spi1 'spi1_cs0_n_px6spi1_cs0_n_px6spi1 'spi1_miso_px7spi1_miso_px7spi1 'ulpi_clk_py0 ulpi_clk_py0uartd 'ulpi_dir_py1 ulpi_dir_py1uartd 'ulpi_nxt_py2 ulpi_nxt_py2uartd 'ulpi_stp_py3 ulpi_stp_py3uartd 'sdmmc1_dat3_py4sdmmc1_dat3_py4sdmmc1 'sdmmc1_dat2_py5sdmmc1_dat2_py5sdmmc1 'sdmmc1_dat1_py6sdmmc1_dat1_py6sdmmc1 'sdmmc1_dat0_py7sdmmc1_dat0_py7sdmmc1 'sdmmc1_clk_pz0sdmmc1_clk_pz0sdmmc1 'sdmmc1_cmd_pz1sdmmc1_cmd_pz1sdmmc1 'lcd_sdin_pz2 lcd_sdin_pz2 displaya 'lcd_wr_n_pz3 lcd_wr_n_pz3 displaya 'lcd_sck_pz4 lcd_sck_pz4 displaya 'sys_clk_req_pz5sys_clk_req_pz5sysclk 'pwr_i2c_scl_pz6pwr_i2c_scl_pz6i2cpwr ';pwr_i2c_sda_pz7pwr_i2c_sda_pz7i2cpwr ';sdmmc4_dat0_paa0sdmmc4_dat0_paa0sdmmc4 'sdmmc4_dat1_paa1sdmmc4_dat1_paa1sdmmc4 'sdmmc4_dat2_paa2sdmmc4_dat2_paa2sdmmc4 'sdmmc4_dat3_paa3sdmmc4_dat3_paa3sdmmc4 'sdmmc4_dat4_paa4sdmmc4_dat4_paa4sdmmc4 'sdmmc4_dat5_paa5sdmmc4_dat5_paa5sdmmc4 'sdmmc4_dat6_paa6sdmmc4_dat6_paa6sdmmc4 'sdmmc4_dat7_paa7sdmmc4_dat7_paa7sdmmc4 'pbb0pbb0i2s4 'cam_i2c_scl_pbb1cam_i2c_scl_pbb1i2c3 ';cam_i2c_sda_pbb2cam_i2c_sda_pbb2i2c3 ';pbb3pbb3vgp3 'pbb4pbb4vgp4 'pbb5pbb5vgp5 'pbb6pbb6vgp6 'pbb7pbb7i2s4 'cam_mclk_pcc0cam_mclk_pcc0vi_alt3 'pcc1pcc1i2s4 'pcc2pcc2i2s4 'sdmmc4_rst_n_pcc3sdmmc4_rst_n_pcc3sdmmc4 'sdmmc4_clk_pcc4sdmmc4_clk_pcc4sdmmc4 'clk2_req_pcc5clk2_req_pcc5dap 'pex_l2_rst_n_pcc6pex_l2_rst_n_pcc6pcie 'pex_l2_clkreq_n_pcc7pex_l2_clkreq_n_pcc7pcie 'pex_l0_prsnt_n_pdd0pex_l0_prsnt_n_pdd0pcie 'pex_l0_rst_n_pdd1pex_l0_rst_n_pdd1pcie 'pex_l0_clkreq_n_pdd2pex_l0_clkreq_n_pdd2pcie 'pex_wake_n_pdd3pex_wake_n_pdd3pcie 'pex_l1_prsnt_n_pdd4pex_l1_prsnt_n_pdd4pcie 'pex_l1_rst_n_pdd5pex_l1_rst_n_pdd5pcie 'pex_l1_clkreq_n_pdd6pex_l1_clkreq_n_pdd6pcie 'pex_l2_prsnt_n_pdd7pex_l2_prsnt_n_pdd7pcie 'clk3_out_pee0clk3_out_pee0 extperiph3 'clk3_req_pee1clk3_req_pee1dev3 'clk1_req_pee2clk1_req_pee2dap 'hdmi_cec_pee3hdmi_cec_pee3cec ';owrowrowr 'sdio3 drive_sdio3Mds.*gpv drive_gpvserial@70006000(nvidia,tegra30-uartnvidia,tegra20-uartp`@ $serialrxtx#okayserial@70006040(nvidia,tegra30-uartnvidia,tegra20-uartp`@@ %serial  rxtx #disabledserial@70006200(nvidia,tegra30-uartnvidia,tegra20-uartpb .77serial  rxtx #disabledserial@70006300(nvidia,tegra30-uartnvidia,tegra20-uartpc ZAAserialrxtx #disabledserial@70006400(nvidia,tegra30-uartnvidia,tegra20-uartpd [BBserialrxtx #disabledgmi@70009000nvidia,tegra30-gmip+H*gmi*gmi #disabledpwm@7000a000&nvidia,tegra30-pwmnvidia,tegra20-pwmppwm #disabledrtc@7000e000&nvidia,tegra30-rtcnvidia,tegra20-rtcp i2c@7000c000&nvidia,tegra30-i2cnvidia,tegra20-i2cp &+ div-clkfast-clk i2crxtx#okayi2c@7000c400&nvidia,tegra30-i2cnvidia,tegra20-i2cp T+6div-clkfast-clk6i2crxtx#okayi2c@7000c500&nvidia,tegra30-i2cnvidia,tegra20-i2cp \+Cdiv-clkfast-clkCi2crxtx#okayi2c@7000c700&nvidia,tegra30-i2cnvidia,tegra20-i2cp x+ggi2cdiv-clkfast-clkrxtx#okay= i2c@7000d000&nvidia,tegra30-i2cnvidia,tegra20-i2cp 5+/div-clkfast-clk/i2crxtx#okayrt5640@1crealtek,rt5640   =#tps65911@2d ti,tps65911- V- .IUa my=!regulatorsvdd1vddio_ddr_1v2OOvdd2 vdd_1v5_gen``=vddctrlvdd_cpu,vdd_sys 51N=vio vdd_1v8_genw@w@= ldo1vdd_pexa,vdd_pexb=ldo2vdd_sata,avdd_plleldo4vdd_rtcOOldo5vddio_sdmmc,avdd_vdacw@2Z=ldo6avdd_dsi_csi,pwrdet_mipiOOldo7vdd_pllm,x,u,a_p_c_sOOldo8 vdd_ddr_hsB@B@tps62361@60 ti,tps62361`tps62361-vout `1i{=spi@7000d400*nvidia,tegra30-slinknvidia,tegra20-slinkp ;+))spirxtx #disabledspi@7000d600*nvidia,tegra30-slinknvidia,tegra20-slinkp R+,,spirxtx #disabledspi@7000d800*nvidia,tegra30-slinknvidia,tegra20-slinkp S+..spirxtx #disabledspi@7000da00*nvidia,tegra30-slinknvidia,tegra20-slinkp ]+DDspirxtx#okay}x@spi-flash@1winbond,w25q32jedec,spi-nor1-spi@7000dc00*nvidia,tegra30-slinknvidia,tegra20-slinkp ^+hhspirxtx #disabledspi@7000de00*nvidia,tegra30-slinknvidia,tegra20-slinkp O+ijspirxtx #disabledkbc@7000e200&nvidia,tegra30-kbcnvidia,tegra20-kbcp U$$kbc #disabledpmc@7000e400nvidia,tegra30-pmcp pclkclk32k_in}#okay.Ha=$memory-controller@7000f000nvidia,tegra30-mcp mc M=memory-controller@7000f400nvidia,tegra30-emcp N9=fuse@7000f800nvidia,tegra30-efusepfuse'fusehda@70030000nvidia,tegra30-hdap Q}ohdahda2hdmihda2codec_2x}ohdahda2hdmihda2codec_2x #disabledahub@70080000nvidia,tegra30-ahubpp gjkd_audioapbifXjk eflmn <d_audioapbifi2s0i2s1i2s2i2s3i2s4dam0dam1dam2spdif@ rx0tx0rx1tx1rx2tx2rx3tx3+i2s@70080300nvidia,tegra30-i2spi2s #disabledi2s@70080400nvidia,tegra30-i2sp  i2s#okay="i2s@70080500nvidia,tegra30-i2spi2s #disabledi2s@70080600nvidia,tegra30-i2speei2s #disabledi2s@70080700nvidia,tegra30-i2spffi2s #disabledmmc@78000000nvidia,tegra30-sdhcix sdhcisdhci#okay  E    mmc@78000200nvidia,tegra30-sdhcix  sdhci sdhci #disabledmmc@78000400nvidia,tegra30-sdhcix EsdhciEsdhci #disabledmmc@78000600nvidia,tegra30-sdhcix sdhcisdhci#okay'usb@7d000000nvidia,tegra30-udc}@ 5utmiusb>X#okay cperipheralusb-phy@7d000000nvidia,tegra30-usb-phy}@}@5utmiregpll_uutmi-padsusbutmi-padskv 3( ;Rh#okay=usb@7d004000nvidia,tegra30-ehciusb-ehci}@@ 5utmi::usbX#okayusb-phy@7d004000nvidia,tegra30-usb-phy}@@}@5utmi:regpll_uutmi-pads:usbutmi-padskv 3( ;R#okay=usb@7d008000nvidia,tegra30-ehciusb-ehci}@ a5utmi;;usbX#okayusb-phy@7d008000nvidia,tegra30-usb-phy}@}@5utmi;regpll_uutmi-pads;usbutmi-padskv3( ;R#okay=cpus+cpu@0cpuarm,cortex-a9=cpu@1cpuarm,cortex-a9=cpu@2cpuarm,cortex-a9=cpu@3cpuarm,cortex-a9= pmuarm,cortex-a9-pmu0 cpu_opp_table0operating-points-v2=opp@51000000,800Z1S 2 E 5 5opp@51000000,850Z S 2 E P Popp@51000000,912ZS 2 E opp@102000000,800Z1Se E 5 5opp@102000000,850Z Se E P Popp@102000000,912ZSe E opp@204000000,800Z1S (k E 5 5opp@204000000,850Z S (k E P Popp@204000000,912ZS (k E opp@312000000,850Z S E P Popp@312000000,912ZS E opp@340000000,800ZSC E 5 5opp@340000000,850ZSC E P Popp@370000000,800Z0lS  E 5 5opp@456000000,850Z S. E P Popp@456000000,912ZS. E opp@475000000,800Z1SO E 5 5opp@475000000,850(ZSO E P Popp@608000000,850ZS$=X E P Popp@608000000,912ZS$=X E opp@620000000,850Z0lS$s E P Popp@640000000,850xZS&% E P Popp@640000000,900ZS&% E opp@760000000,850PZ4aS-L E P Popp@760000000,900hZS-L E opp@760000000,912ZS-L E opp@760000000,975ZS-L Eopp@816000000,850ZS0, E P Popp@816000000,912ZS0, E opp@860000000,850Z S3B E P Popp@860000000,900xZS3B E opp@860000000,9758ZS3B Eopp@860000000,1000ZS3B EB@B@opp@910000000,900Z0`S6= E opp@1000000000,900Z S; E opp@1000000000,975xZS; Eopp@1000000000,1000ZS; EB@B@opp@1000000000,1025ZS; Eopp@1100000000,900ZSA E opp@1100000000,975HZSA Eopp@1100000000,10008ZSA EB@B@opp@1100000000,1025ZSA Eopp@1100000000,1075ZSA Eg8g8opp@1150000000,975Z0`SD Eopp@1200000000,975ZSG Eopp@1200000000,1000HZSG EB@B@opp@1200000000,10258ZSG Eopp@1200000000,1050ZSG Eopp@1200000000,1075ZSG Eg8g8opp@1200000000,1100ZSG Eopp@1300000000,1000ZSM|m EB@B@opp@1300000000,1025 ZSM|m Eopp@1300000000,1050XZ0a @ SM|m Eopp@1300000000,1075 ZSM|m Eg8g8opp@1300000000,1100ZSM|m Eopp@1300000000,1125ZSM|m E**opp@1300000000,1150ZSM|m E00opp@1300000000,1175ZSM|m Eopp@1400000000,1100Z0|SSrN Eopp@1400000000,1125Z SSrN E**opp@1400000000,1150Z SSrN E00opp@1400000000,1175ZSSrN Eopp@1400000000,1237ZSSrN Eopp@1500000000,1125(Z @ SYh/ E**opp@1500000000,1150(Z @ SYh/ E00opp@1500000000,1200ZSYh/ EOOopp@1500000000,1237ZSYh/ Eopp@1600000000,1212Z0`S_^ E~`~`opp@1600000000,1237Z0`S_^ Eopp@1700000000,1212Z0`SeS E~`~`opp@1700000000,1237Z0`SeS Ealiases/i2c@7000d000/tps65911@2d/rtc@7000e000/serial@70006000chosenserial0:115200n8clock@0 fixed-clock}=gpio-leds gpio-ledsgpled1LED1  Ygpled2LED2  Xregulator@0regulator-fixed vdd_5v_inLK@LK@=regulator@1regulator-fixedchargepump_5vLK@LK@i !regulator@2regulator-fixedvdd_ddr``i ! regulator@3regulator-fixed vdd_5v_sataLK@LK@i   regulator@4regulator-fixed usb1_vbusLK@LK@    regulator@5regulator-fixed usb3_vbusLK@LK@    =regulator@6regulator-fixedsys_3v3,vdd_3v3_alw2Z2Zi ! =regulator@7regulator-fixed sys_3v3_pexs2Z2Zi  _ =regulator@8regulator-fixed +VDD_5V_HDMILK@LK@i = sound;nvidia,tegra-audio-rt5640-beavernvidia,tegra-audio-rt5640 NVIDIA Tegra Beaver@ +HeadphonesHPORHeadphonesHPOLMic JackMICBIAS1IN2PMic Jack @" V# i $pll_apll_a_out0mclk }x$ x compatibleinterrupt-parent#address-cells#size-cellsmodelphandleopp-microvoltopp-hzopp-supported-hwopp-suspendopp-peak-kBpsdevice_typeregreg-namesinterruptsinterrupt-names#interrupt-cellsinterrupt-map-maskinterrupt-mapbus-rangerangesclocksclock-namesresetsreset-namesstatusavdd-pexa-supplyavdd-pexb-supplyavdd-pex-pll-supplyavdd-plle-supplyvddio-pex-ctl-supplyhvdd-pex-supplyassigned-addressesnvidia,num-lanespooliommusnvidia,headinterconnectsinterconnect-nameshdmi-supplyvdd-supplynvidia,hpd-gpionvidia,ddc-i2c-businterrupt-controllerarm,data-latencyarm,tag-latencycache-unifiedcache-level#clock-cells#reset-cells#dma-cellsoperating-points-v2#gpio-cellsgpio-controllerirampinctrl-namespinctrl-0nvidia,pinsnvidia,functionnvidia,pullnvidia,tristatenvidia,enable-inputnvidia,open-drainnvidia,high-speed-modenvidia,schmittnvidia,pull-down-strengthnvidia,pull-up-strengthnvidia,slew-rate-risingnvidia,slew-rate-fallingreg-shiftdmasdma-names#pwm-cellsclock-frequencyrealtek,ldo1-en-gpioswakeup-sourceti,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-coupled-withregulator-coupled-max-spreadregulator-max-step-microvoltnvidia,tegra-cpu-regulatorregulator-boot-onti,vsel0-state-highti,vsel1-state-highnvidia,tegra-core-regulatorspi-max-frequencynvidia,invert-interruptnvidia,suspend-modenvidia,cpu-pwr-good-timenvidia,cpu-pwr-off-timenvidia,core-pwr-good-timenvidia,core-pwr-off-timenvidia,core-power-req-active-highnvidia,sys-clock-req-active-high#iommu-cells#interconnect-cellsnvidia,memory-controllernvidia,ahub-cif-idsvqmmc-supplycd-gpioswp-gpiospower-gpiosbus-widthnon-removablephy_typenvidia,needs-double-resetnvidia,phydr_mode#phy-cellsnvidia,hssync-start-delaynvidia,idle-wait-delaynvidia,elastic-limitnvidia,term-range-adjnvidia,xcvr-setupnvidia,xcvr-setup-use-fusesnvidia,xcvr-lsfslewnvidia,xcvr-lsrslewnvidia,xcvr-hsslewnvidia,hssquelch-levelnvidia,hsdiscon-levelnvidia,has-utmi-pad-registersvbus-supplycpu-supplyinterrupt-affinityopp-sharedclock-latency-nsrtc0rtc1serial0stdout-pathlabelenable-active-highvin-supplygpio-open-drainnvidia,modelnvidia,audio-routingnvidia,i2s-controllernvidia,audio-codecnvidia,hp-det-gpiosassigned-clocksassigned-clock-parents