\8V(V,mecer,xms6rockchip,rk32297Mecer Xtreme Mini S6aliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000Z/mmc@30000000_/mmc@30010000d/mmc@30020000cpuscpu@f00icpu,arm,cortex-a7uy@pscicpu@f01icpu,arm,cortex-a7uypscicpu@f02icpu,arm,cortex-a7uypscicpu@f03icpu,arm,cortex-a7uypsciopp_table0,operating-points-v2opp-408000000Q~@ opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxopp-1296000000M?d7opp-1392000000R<opp-1464000000WB\arm-pmu,arm,cortex-a7-pmu0LMNO!psci,arm,psci-1.0arm,psci-0.2smctimer,arm,armv7-timer40   Xn6oscillator ,fixed-clockXn6hxin24m{"display-subsystem,rockchip,display-subsystem i2s1@100b0000(,rockchip,rk3228-i2srockchip,rk3066-i2su @ i2s_clki2s_hclkQ  txrxdefault  disabledi2s0@100c0000(,rockchip,rk3228-i2srockchip,rk3066-i2su @ i2s_clki2s_hclkP txrx disabledspdif@100d0000,rockchip,rk3228-spdifu  S mclkhclk txdefault  disabledi2s2@100e0000(,rockchip,rk3228-i2srockchip,rk3066-i2su@ i2s_clki2s_hclkR txrx disabledsyscon@11000000&,rockchip,rk3228-grfsysconsimple-mfdu#io-domains",rockchip,rk3228-io-voltage-domainokay  usb2-phy@760,rockchip,rk3228-usb2phyu` phyclk husb480m_phy0{okay<otg-port$;<=otg-bvalidotg-idlinestateokay ;host-port > linestateokay =usb2-phy@800,rockchip,rk3228-usb2phyu phyclk husb480m_phy1{okay>otg-port D linestateokay ?host-port E linestateokay @serial@11010000,snps,dw-apb-uartu 7Xn6MUbaudclkapb_pclkdefault " disabledserial@11020000,snps,dw-apb-uartu 8Xn6NVbaudclkapb_pclkdefault" disabledserial@11030000,snps,dw-apb-uartu 9Xn6OWbaudclkapb_pclkdefault"okayefuse@11040000,rockchip,rk3228-efuseu G pclk_efuseid@7ucpu_leakage@17ui2c@11050000,rockchip,rk3228-i2cu $i2cLdefault disabledi2c@11060000,rockchip,rk3228-i2cu %i2cMdefault disabledi2c@11070000,rockchip,rk3228-i2cu &i2cNdefault disabledi2c@11080000,rockchip,rk3228-i2cu 'i2cOdefault disabledspi@11090000,rockchip,rk3228-spiu  1ARspiclkapb_pclkdefault disabledwatchdog@110a0000 ,rockchip,rk3228-wdtsnps,dw-wdtu  (b disabledpwm@110b0000,rockchip,rk3288-pwmu /^pwmdefault disabledpwm@110b0010,rockchip,rk3288-pwmu /^pwmdefaultokayLpwm@110b0020,rockchip,rk3288-pwmu /^pwmdefault okayMpwm@110b0030,rockchip,rk3288-pwmu 0/^pwmdefault! disabledtimer@110c0000,,rockchip,rk3228-timerrockchip,rk3288-timeru  + "a timerpclkclock-controller@110e0000,rockchip,rk3228-cruu:#{GHTkb$d#g0,eррxhррxhpdma@110f0000,arm,pl330arm,primecellu@y apb_pclk thermal-zonescpu-thermald$tripscpu_alert0pppassive%cpu_alert1$ppassive&cpu_crit_ pcriticalcooling-mapsmap0%0map1&0tsadc@11150000,rockchip,rk3228-tsadcu :HXtsadcapb_pclkTHdyW tsadc-apbinitdefaultsleep'('0sokayG$hdmi-phy@12030000,rockchip,rk3228-hdmi-phyum"sysclkrefoclkrefpclk{ hhdmiphy_phyokay,gpu@20000000",rockchip,rk3228-maliarm,mali-400u Hgpgpmmupp0ppmmu0pp1ppmmu1 buscorey~okay^)iommu@20020800,rockchip,iommuu    aclkifacej disablediommu@20030480,rockchip,iommuu @ @  aclkifacej disabledvop@20050000,rockchip,rk3228-vopu   aclk_vopdclk_vophclk_vopydef axiahbdclkw*okayport endpoint@0u~+0iommu@20053f00,rockchip,iommuu ?   aclkifacejokay*rga@20060000(,rockchip,rk3228-rgarockchip,rk3288-rgau  !aclkhclksclkykmn coreaxiahbiommu@20070800,rockchip,iommuu   aclkifacejokayhdmi@200a0000,rockchip,rk3228-dw-hdmiu " #T,{lisfriahbcecdefault -./y`hdmi,hdmi:#okayportsportendpoint@0u~0+mmc@300000000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcu0@   Drvbiuciuciu-driveciu-sampledefault 123okaymmc@300100000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcu0@   Eswbiuciuciu-driveciu-sampledefault 456okay7mmc@300200000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcu0@ X<4`*<4` Guybiuciuciu-driveciu-sample8default 89:ySresetokayusb@300400002,rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2u0 otgVotg^p@ ; usb2-phyokayusb@30080000 ,generic-ehciu0  <=usbokayusb@300a0000 ,generic-ohciu0   <=usbokayusb@300c0000 ,generic-ehciu0   >?usbokayusb@300e0000 ,generic-ohciu0  >?usbokayusb@30100000 ,generic-ehciu0 B >@usbokayusb@30120000 ,generic-ohciu0 C >@usbokayethernet@30200000,rockchip,rk3228-gmacu0  macirq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macy8 stmmaceth:#okayT|doutputArmii Bmdio,snps,dwmac-mdioethernet-phy@04,ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22uy?Ainterrupt-controller@32010000 ,arm,gic-400 u22 2@ 2`   pinctrl,rockchip,rk3228-pinctrl:#gpio0@11110000,rockchip,gpio-banku 3@gpio1@11120000,rockchip,gpio-banku 4Agpio2@11130000,rockchip,gpio-banku 5BHgpio3@11140000,rockchip,gpio-banku 6CGpcfg-pull-up Fpcfg-pull-downEpcfg-pull-none&Dpcfg-pull-none-drv-12ma3 Csdmmcsdmmc-clkBC1sdmmc-cmdBC2sdmmc-bus4@BCCCC3sdiosdio-clkBC4sdio-cmdBC5sdio-bus4@BCCCC6emmcemmc-clkBD8emmc-cmdBD9emmc-bus8BDDDDDDDD:gmacrgmii-pinsBD DDCCCC C CDDDD DDrmii-pinsBD DDCC CDDDDphy-pins BDDhdmihdmi-hpdBE.hdmii2c-xfer BDD-hdmi-cecBD/i2c0i2c0-xfer BDDi2c1i2c1-xfer BDDi2c2i2c2-xfer BDDi2c3i2c3-xfer BDDspi0spi0-clkB Fspi0-cs0BFspi0-txB Fspi0-rxB Fspi0-cs1B Fspi1spi1-clkBFspi1-cs0BFspi1-rxBFspi1-txBFspi1-cs1BFi2s1i2s1-busBD D D D DDDDD pwm0pwm0-pinBDpwm1pwm1-pinBDpwm2pwm2-pinB D pwm3pwm3-pinB D!spdifspdif-txBD tsadcotp-pinBD'otp-outBD(uart0uart0-xfer BDDuart0-ctsBDuart0-rtsBDuart1uart1-xfer B D Duart1-ctsBDuart1-rtsB Duart2uart2-xfer BFDuart21-xfer B F Duart2-ctsBDuart2-rtsBDusbhost-vbus-drvBDImemory@60000000imemoryu`@dc-12v-regulator,regulator-fixedPdc_12v_sKext_gmac ,fixed-clockXsY@ hext_gmac{power-led ,gpio-ledsled-0 Gonsdio-pwrseq,mmc-pwrseq-simpleHH7vcc-host-regulator,regulator-fixed GdefaultI Pvcc_host_sJvcc-phy-regulator,regulator-fixedPvcc_phyw@w@_sBvcc-sys-regulator,regulator-fixedPvcc_sys_sLK@LK@KJvccio-1v8-regulator,regulator-fixed Pvccio_1v8w@w@_Jvccio-3v3-regulator,regulator-fixed Pvccio_3v32Z2Z_J vdd-arm-regulator,pwm-regulatorLaJPvdd_arm~\_svdd-log-regulator,pwm-regulatorMaJPvdd_logB@ _s) #address-cells#size-cellsinterrupt-parentcompatiblemodelserial0serial1serial2spi0mmc0mmc1mmc2device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsclock-namesdmasdma-namespinctrl-namespinctrl-0statusvccio1-supplyvccio2-supplyvccio4-supplyinterrupt-names#phy-cellsphy-supplyreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-rates#dma-cellsarm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-modemali-supply#iommu-cellsiommusremote-endpointassigned-clock-parentsphysphy-namesfifo-depthcap-mmc-highspeeddisable-wpbus-widthcap-sd-highspeedcap-sdio-irqmmc-pwrseqnon-removablevqmmc-supplymax-frequencyrockchip,default-sample-phasedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-handlephy-modephy-is-integratedinterrupt-controller#interrupt-cellsrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltgpiosdefault-statereset-gpiosenable-active-highgpiovin-supplypwmspwm-supply