\*8V,(U$,rockchip,rk3229-evbrockchip,rk3229!7Rockchip RK3229 Evaluation boardaliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000Z/mmc@30020000cpuscpu@f00_cpu,arm,cortex-a7kov@pscicpu@f01_cpu,arm,cortex-a7kovpscicpu@f02_cpu,arm,cortex-a7kovpscicpu@f03_cpu,arm,cortex-a7kovpsciopp_table0,operating-points-v2opp-408000000Q~@opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxopp-1296000000M?d7opp-1392000000R<opp-1464000000WB\arm-pmu,arm,cortex-a7-pmu0 LMNOpsci,arm,psci-1.0arm,psci-0.2smctimer,arm,armv7-timer*0    Nn6oscillator ,fixed-clockNn6^xin24mq"display-subsystem,rockchip,display-subsystem~ i2s1@100b0000(,rockchip,rk3228-i2srockchip,rk3066-i2sk @  i2s_clki2s_hclkQ  txrxdefault  disabledi2s0@100c0000(,rockchip,rk3228-i2srockchip,rk3066-i2sk @  i2s_clki2s_hclkP txrx disabledspdif@100d0000,rockchip,rk3228-spdifk   S mclkhclk txdefault  disabledi2s2@100e0000(,rockchip,rk3228-i2srockchip,rk3066-i2sk@  i2s_clki2s_hclkR txrx disabledsyscon@11000000&,rockchip,rk3228-grfsysconsimple-mfdk#io-domains",rockchip,rk3228-io-voltage-domainokay  usb2-phy@760,rockchip,rk3228-usb2phyk` phyclk ^usb480m_phy0qokay:otg-port$ ;<=otg-bvalidotg-idlinestateokay9host-port  > linestateokay;usb2-phy@800,rockchip,rk3228-usb2phyk phyclk ^usb480m_phy1qokay<otg-port  D linestateokay=host-port  E linestateokay>serial@11010000,snps,dw-apb-uartk  7Nn6MUbaudclkapb_pclkdefault  disabledserial@11020000,snps,dw-apb-uartk  8Nn6NVbaudclkapb_pclkdefault disabledserial@11030000,snps,dw-apb-uartk  9Nn6OWbaudclkapb_pclkdefaultokayefuse@11040000,rockchip,rk3228-efusek G pclk_efuseid@7kcpu_leakage@17ki2c@11050000,rockchip,rk3228-i2ck  $i2cLdefault disabledi2c@11060000,rockchip,rk3228-i2ck  %i2cMdefault disabledi2c@11070000,rockchip,rk3228-i2ck  &i2cNdefault disabledi2c@11080000,rockchip,rk3228-i2ck  'i2cOdefault disabledspi@11090000,rockchip,rk3228-spik   1ARspiclkapb_pclkdefault disabledwatchdog@110a0000 ,rockchip,rk3228-wdtsnps,dw-wdtk   (b disabledpwm@110b0000,rockchip,rk3288-pwmk %^pwmdefault disabledpwm@110b0010,rockchip,rk3288-pwmk %^pwmdefaultokayKpwm@110b0020,rockchip,rk3288-pwmk %^pwmdefault okayLpwm@110b0030,rockchip,rk3288-pwmk 0%^pwmdefault! disabledtimer@110c0000,,rockchip,rk3228-timerrockchip,rk3288-timerk   + "a timerpclkclock-controller@110e0000,rockchip,rk3228-cruk0#q=HJkb$Z#g0,eррxhррxhpdma@110f0000,arm,pl330arm,primecellk@ oz apb_pclk thermal-zonescpu-thermald$tripscpu_alert0pfpassive%cpu_alert1$fpassive&cpu_crit_ fcriticalcooling-mapsmap0%0map1&0tsadc@11150000,rockchip,rk3228-tsadck  :HXtsadcapb_pclkJHZoW tsadc-apbinitdefaultsleep'('&sokay=$hdmi-phy@12030000,rockchip,rk3228-hdmi-phykm"sysclkrefoclkrefpclkq ^hdmiphy_phy disabled+gpu@20000000",rockchip,rk3228-maliarm,mali-400k H gpgpmmupp0ppmmu0pp1ppmmu1 buscoreo~ disablediommu@20020800,rockchip,iommuk    aclkifaceT disablediommu@20030480,rockchip,iommuk @ @   aclkifaceT disabledvop@20050000,rockchip,rk3228-vopk   aclk_vopdclk_vophclk_vopodef axiahbdclka) disabledport endpoint@0kh*/iommu@20053f00,rockchip,iommuk ?   aclkifaceT disabled)rga@20060000(,rockchip,rk3228-rgarockchip,rk3288-rgak   !aclkhclksclkokmn coreaxiahbiommu@20070800,rockchip,iommuk    aclkifaceT disabledhdmi@200a0000,rockchip,rk3228-dw-hdmik   #Jx+{lisfriahbcecdefault ,-.o`hdmi+hdmi0# disabledportsportendpoint@0kh/*mmc@300000000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshck0@   Drvbiuciuciu-driveciu-sampledefault 012 disabledmmc@300100000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshck0@   Eswbiuciuciu-driveciu-sampledefault 345 disabledmmc@300200000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshck0@  N<4`<4` Guybiuciuciu-driveciu-sampledefault 678oSresetokayusb@300400002,rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2k0  otgotg(@ 9 usb2-phyokayusb@30080000 ,generic-ehcik0   :;usbokayusb@300a0000 ,generic-ohcik0    :;usbokayusb@300c0000 ,generic-ehcik0    <=usbokayusb@300e0000 ,generic-ohcik0   <=usbokayusb@30100000 ,generic-ehcik0  B <>usbokayusb@30120000 ,generic-ohcik0  C <>usbokayethernet@30200000,rockchip,rk3228-gmack0   macirq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_maco8 stmmaceth0#okayJ}~ x?}7input@DrgmiidefaultA MB] s'B@0interrupt-controller@32010000 ,arm,gic-400 k22 2@ 2`    pinctrl,rockchip,rk3228-pinctrl0#gpio0@11110000,rockchip,gpio-bankk  3@gpio1@11120000,rockchip,gpio-bankk  4Agpio2@11130000,rockchip,gpio-bankk  5BBgpio3@11140000,rockchip,gpio-bankk  6CGpcfg-pull-upFpcfg-pull-downEpcfg-pull-noneDpcfg-pull-none-drv-12ma Csdmmcsdmmc-clkC0sdmmc-cmdC1sdmmc-bus4@CCCC2sdiosdio-clkC3sdio-cmdC4sdio-bus4@CCCC5emmcemmc-clkD6emmc-cmdD7emmc-bus8DDDDDDDD8gmacrgmii-pinsD DDCCCC C CDDDD DDArmii-pinsD DDCC CDDDDphy-pins DDhdmihdmi-hpdE-hdmii2c-xfer DD,hdmi-cecD.i2c0i2c0-xfer DDi2c1i2c1-xfer DDi2c2i2c2-xfer DDi2c3i2c3-xfer DDspi0spi0-clk Fspi0-cs0Fspi0-tx Fspi0-rx Fspi0-cs1 Fspi1spi1-clkFspi1-cs0Fspi1-rxFspi1-txFspi1-cs1Fi2s1i2s1-busD D D D DDDDD pwm0pwm0-pinDpwm1pwm1-pinDpwm2pwm2-pin D pwm3pwm3-pin D!spdifspdif-txD tsadcotp-pinD'otp-outD(uart0uart0-xfer DDuart0-ctsDuart0-rtsDuart1uart1-xfer  D Duart1-ctsDuart1-rts Duart2uart2-xfer FDuart21-xfer  F Duart2-ctsDuart2-rtsDkeyspwr-keyFMusbhost-vbus-drvDHmemory@60000000_memoryk`@dc-12v-regulator,regulator-fixed)dc_12v8L^vJext_gmac ,fixed-clockNsY@ ^ext_gmacq?vcc-host-regulator,regulator-fixed XGdefaultH )vcc_host8LIvcc-phy-regulator,regulator-fixed)vcc_phy^w@vw@8L@vcc-sys-regulator,regulator-fixed)vcc_sys8L^LK@vLK@JIvccio-1v8-regulator,regulator-fixed )vccio_1v8^w@vw@8Ivccio-3v3-regulator,regulator-fixed )vccio_3v3^2Zv2Z8I vdd-arm-regulator,pwm-regulatorKaI)vdd_arm^~v\8Lvdd-log-regulator,pwm-regulatorLaI)vdd_log^B@v 8Lgpio_keys ,gpio-keysdefaultMpower-keyGPIO Key Power Gtd #address-cells#size-cellsinterrupt-parentcompatiblemodelserial0serial1serial2spi0mmc0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsclock-namesdmasdma-namespinctrl-namespinctrl-0statusvccio1-supplyvccio2-supplyvccio4-supplyinterrupt-names#phy-cellsphy-supplyreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-rates#dma-cellsarm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-mode#iommu-cellsiommusremote-endpointassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeednon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayinterrupt-controller#interrupt-cellsrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltenable-active-highvin-supplypwmspwm-supplyautorepeatlabelgpioslinux,codedebounce-intervalwakeup-source