T78N(oN!,Rockchip RK3228 Evaluation board$2rockchip,rk3228-evbrockchip,rk3228aliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000Z/mmc@30020000cpuscpu@f00_cpu2arm,cortex-a7kov@pscicpu@f01_cpu2arm,cortex-a7kovpscicpu@f02_cpu2arm,cortex-a7kovpscicpu@f03_cpu2arm,cortex-a7kovpsciopp_table02operating-points-v2opp-408000000Q~@opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxarm-pmu2arm,cortex-a7-pmu0LMNO psci2arm,psci-1.0arm,psci-0.2smctimer2arm,armv7-timer0   Cn6oscillator 2fixed-clockCn6Sxin24mfdisplay-subsystem2rockchip,display-subsystemsi2s1@100b0000(2rockchip,rk3228-i2srockchip,rk3066-i2sk @ yi2s_clki2s_hclkQ  txrxdefault  disabledi2s0@100c0000(2rockchip,rk3228-i2srockchip,rk3066-i2sk @ yi2s_clki2s_hclkP txrx disabledspdif@100d00002rockchip,rk3228-spdifk  S ymclkhclk txdefault  disabledi2s2@100e0000(2rockchip,rk3228-i2srockchip,rk3066-i2sk@ yi2s_clki2s_hclkR txrx disabledsyscon@11000000&2rockchip,rk3228-grfsysconsimple-mfdkio-domains"2rockchip,rk3228-io-voltage-domain disabledusb2-phy@7602rockchip,rk3228-usb2phyk` yphyclk Susb480m_phy0f disabled6otg-port$;<=otg-bvalidotg-idlinestate disabled5host-port > linestate disabled7usb2-phy@8002rockchip,rk3228-usb2phyk yphyclk Susb480m_phy1f disabled8otg-port D linestate disabled9host-port E linestate disabled:serial@110100002snps,dw-apb-uartk 7Cn6MUybaudclkapb_pclkdefault   disabledserial@110200002snps,dw-apb-uartk 8Cn6NVybaudclkapb_pclkdefault disabledserial@110300002snps,dw-apb-uartk 9Cn6OWybaudclkapb_pclkdefaultokayefuse@110400002rockchip,rk3228-efusek G ypclk_efuseid@7kcpu_leakage@17ki2c@110500002rockchip,rk3228-i2ck $yi2cLdefault disabledi2c@110600002rockchip,rk3228-i2ck %yi2cMdefault disabledi2c@110700002rockchip,rk3228-i2ck &yi2cNdefault disabledi2c@110800002rockchip,rk3228-i2ck 'yi2cOdefault disabledspi@110900002rockchip,rk3228-spik  1ARyspiclkapb_pclkdefault disabledwatchdog@110a0000 2rockchip,rk3228-wdtsnps,dw-wdtk  (b disabledpwm@110b00002rockchip,rk3288-pwmk ^ypwmdefault disabledpwm@110b00102rockchip,rk3288-pwmk ^ypwmdefault disabledpwm@110b00202rockchip,rk3288-pwmk ^ypwmdefault disabledpwm@110b00302rockchip,rk3288-pwmk 0^ypwmdefault disabledtimer@110c0000,2rockchip,rk3228-timerrockchip,rk3288-timerk  + a ytimerpclkclock-controller@110e00002rockchip,rk3228-crukfH kb$#g0,eррxhррxhpdma@110f00002arm,pl330arm,primecellk@/: yapb_pclk thermal-zonescpu-thermalQdgu tripscpu_alert0pfpassive!cpu_alert1$fpassive"cpu_crit_ fcriticalcooling-mapsmap0!0map1"0tsadc@111500002rockchip,rk3228-tsadck :HXytsadcapb_pclk HoW tsadc-apbinitdefaultsleep#$#sokay hdmi-phy@120300002rockchip,rk3228-hdmi-phykmysysclkrefoclkrefpclkf Shdmiphy_phy disabled'gpu@20000000"2rockchip,rk3228-maliarm,mali-400k Hgpgpmmupp0ppmmu0pp1ppmmu1 ybuscoreo~ disablediommu@200208002rockchip,iommuk    yaclkiface/ disablediommu@200304802rockchip,iommuk @ @  yaclkiface/ disabledvop@200500002rockchip,rk3228-vopk   yaclk_vopdclk_vophclk_vopodef axiahbdclk<% disabledportendpoint@0kC&+iommu@20053f002rockchip,iommuk ?   yaclkiface/ disabled%rga@20060000(2rockchip,rk3228-rgarockchip,rk3288-rgak  !yaclkhclksclkokmn coreaxiahbiommu@200708002rockchip,iommuk   yaclkiface/ disabledhdmi@200a00002rockchip,rk3228-dw-hdmik  # S'{lyisfriahbcecdefault ()*o`hdmij'ohdmi disabledportsportendpoint@0kC+&mmc@3000000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshck0@   Drvybiuciuciu-driveciu-sampleydefault ,-. disabledmmc@3001000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshck0@   Eswybiuciuciu-driveciu-sampleydefault /01 disabledmmc@3002000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshck0@ C<4`<4` Guyybiuciuciu-driveciu-sampleydefault 234oSresetokayusb@3004000022rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2k0 yotgotg @ j5 ousb2-phy disabledusb@30080000 2generic-ehcik0  6j7ousb disabledusb@300a0000 2generic-ohcik0   6j7ousb disabledusb@300c0000 2generic-ehcik0   8j9ousb disabledusb@300e0000 2generic-ohcik0  8j9ousb disabledusb@30100000 2generic-ehcik0 B 8j:ousb disabledusb@30120000 2generic-ohcik0 C 8j:ousb disabledethernet@302000002rockchip,rk3228-gmack0  macirq8~oMystmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_maco8 stmmacethokay |*output7;BrmiiK<mdio2snps,dwmac-mdioethernet-phy@042ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22ko?V<interrupt-controller@32010000 2arm,gic-400h} k22 2@ 2`   pinctrl2rockchip,rk3228-pinctrlgpio0@111100002rockchip,gpio-bankk 3@h}gpio1@111200002rockchip,gpio-bankk 4Ah}gpio2@111300002rockchip,gpio-bankk 5Bh}gpio3@111400002rockchip,gpio-bankk 6Ch}pcfg-pull-up@pcfg-pull-down?pcfg-pull-none>pcfg-pull-none-drv-12ma =sdmmcsdmmc-clk=,sdmmc-cmd=-sdmmc-bus4@====.sdiosdio-clk=/sdio-cmd=0sdio-bus4@====1emmcemmc-clk>2emmc-cmd>3emmc-bus8>>>>>>>>4gmacrgmii-pins> >>==== = =>>>> >>rmii-pins> >>== =>>>>phy-pins >>hdmihdmi-hpd?)hdmii2c-xfer >>(hdmi-cec>*i2c0i2c0-xfer >>i2c1i2c1-xfer >>i2c2i2c2-xfer >>i2c3i2c3-xfer >>spi0spi0-clk @spi0-cs0@spi0-tx @spi0-rx @spi0-cs1 @spi1spi1-clk@spi1-cs0@spi1-rx@spi1-tx@spi1-cs1@i2s1i2s1-bus> > > > >>>>> pwm0pwm0-pin>pwm1pwm1-pin>pwm2pwm2-pin >pwm3pwm3-pin >spdifspdif-tx> tsadcotp-pin>#otp-out>$uart0uart0-xfer >> uart0-cts> uart0-rts>uart1uart1-xfer  > >uart1-cts>uart1-rts >uart2uart2-xfer @>uart21-xfer  @ >uart2-cts>uart2-rts>memory@60000000_memoryk`@vcc-phy-regulator2regulator-fixed vcc_phyw@1w@I]; #address-cells#size-cellsinterrupt-parentmodelcompatibleserial0serial1serial2spi0mmc0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsclock-namesdmasdma-namespinctrl-namespinctrl-0statusinterrupt-names#phy-cellsreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-rates#dma-cellsarm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarity#iommu-cellsiommusremote-endpointassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeedmmc-ddr-1_8vdisable-wpnon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-supplyphy-modephy-handlephy-is-integratedinterrupt-controller#interrupt-cellsrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsenable-active-highregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-on