b8W( V"ti,omap4-sdpti,omap4430ti,omap4 +7TI OMAP4 SDP boardchosenaliases?=/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0?B/ocp/interconnect@48000000/segment@0/target-module@72000/i2c@0?G/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0EL/ocp/interconnect@48000000/segment@200000/target-module@150000/i2c@0?Q/ocp/interconnect@48000000/segment@0/target-module@9c000/mmc@0?V/ocp/interconnect@48000000/segment@0/target-module@b4000/mmc@0?[/ocp/interconnect@48000000/segment@0/target-module@ad000/mmc@0?`/ocp/interconnect@48000000/segment@0/target-module@d1000/mmc@0?e/ocp/interconnect@48000000/segment@0/target-module@d5000/mmc@0Bj/ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0Br/ocp/interconnect@48000000/segment@0/target-module@6c000/serial@0Bz/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0B/ocp/interconnect@48000000/segment@0/target-module@6e000/serial@0 /ocp/dsp/ocp/ipu@55020000G/ocp/target-module@58000000/dss@0/target-module@4000/encoder@0/panel@0G/ocp/target-module@58000000/dss@0/target-module@5000/encoder@0/panel@0 /connectorcpus+cpu@0arm,cortex-a9cpucpu  'O 5acpu@1arm,cortex-a9cpusram@40304000 mmio-sram@0@interrupt-controller@48241000arm,cortex-a9-gic2H$H$ cache-controller@48242000arm,pl310-cacheH$ CQlocal-timer@48240600arm,cortex-a9-twd-timerH$  ]  interrupt-controller@48281000ti,omap4-wugen-mpu2H( ocpsimple-pm-bush$ +vl3-noc@44000000ti,omap4-l3-nocDD E]  interconnect@4a300000ti,omap4-l4-wkupsimple-pm-bush  fckJ0J0J0 }aplaia0+$vJ0J1J2segment@0simple-pm-bus+v`` @@PPtarget-module@4000ti,sysc-omap2ti,sysc@@ }revsysc 0fck+ v@counter@0ti,omap-counter32k target-module@6000ti,sysc-omap4ti,sysc`}rev+ v` prm@0ti,omap4-prmsimple-bus  ] + v clocks+sys_clkin_ck@110 ti,mux-clock abe_dpll_bypass_clk_mux_ck@108 ti,mux-clock9abe_dpll_refclk_mux_ck@10c ti,mux-clock 8dbgclk_mux_ckfixed-factor-clockl4_wkup_clk_mux_ck@108 ti,mux-clocksyc_clk_div_ck@100ti,divider-clockusim_ck@1858ti,divider-clockXusim_fclk@1858ti,gate-clockXtrace_clk_div_ckti,clkdm-gate-clock bandgap_fclk@1888ti,gate-clockclockdomainsemu_sys_clkdmti,clockdomainl4_wkup_cm@1800 ti,omap4-cm+ vclk@20 ti,clkctrl \ emu_sys_cm@1a00 ti,omap4-cm+ vclk@20 ti,clkctrl prm@300#ti,omap4-prm-instti,omap-prm-instprm@400#ti,omap4-prm-instti,omap-prm-instcprm@500#ti,omap4-prm-instti,omap-prm-instprm@600#ti,omap4-prm-instti,omap-prm-instprm@700#ti,omap4-prm-instti,omap-prm-inst4prm@f00#ti,omap4-prm-instti,omap-prm-instprm@1000#ti,omap4-prm-instti,omap-prm-instprm@1100#ti,omap4-prm-instti,omap-prm-inst@prm@1200#ti,omap4-prm-instti,omap-prm-instprm@1300#ti,omap4-prm-instti,omap-prm-instprm@1400#ti,omap4-prm-instti,omap-prm-instprm@1600#ti,omap4-prm-instti,omap-prm-instprm@1700#ti,omap4-prm-instti,omap-prm-inst prm@1900#ti,omap4-prm-instti,omap-prm-instprm@1b00#ti,omap4-prm-instti,omap-prm-inst@target-module@a000ti,sysc-omap4ti,sysc}rev+ vscrm@0ti,omap4-scrm clocks+auxclk0_src_gate_ck@310 ti,composite-no-wait-gate-clockauxclk0_src_mux_ck@310ti,composite-mux-clock auxclk0_src_ckti,composite-clockauxclk0_ck@310ti,divider-clock.auxclk1_src_gate_ck@314 ti,composite-no-wait-gate-clockauxclk1_src_mux_ck@314ti,composite-mux-clock  auxclk1_src_ckti,composite-clock !auxclk1_ck@314ti,divider-clock!/auxclk2_src_gate_ck@318 ti,composite-no-wait-gate-clock"auxclk2_src_mux_ck@318ti,composite-mux-clock #auxclk2_src_ckti,composite-clock"#$auxclk2_ck@318ti,divider-clock$0auxclk3_src_gate_ck@31c ti,composite-no-wait-gate-clock%auxclk3_src_mux_ck@31cti,composite-mux-clock &auxclk3_src_ckti,composite-clock%&'auxclk3_ck@31cti,divider-clock'1auxclk4_src_gate_ck@320 ti,composite-no-wait-gate-clock (auxclk4_src_mux_ck@320ti,composite-mux-clock  )auxclk4_src_ckti,composite-clock()*auxclk4_ck@320ti,divider-clock* 2auxclk5_src_gate_ck@324 ti,composite-no-wait-gate-clock$+auxclk5_src_mux_ck@324ti,composite-mux-clock $,auxclk5_src_ckti,composite-clock+,-auxclk5_ck@324ti,divider-clock-$3auxclkreq0_ck@210 ti,mux-clock./0123auxclkreq1_ck@214 ti,mux-clock./0123auxclkreq2_ck@218 ti,mux-clock./0123auxclkreq3_ck@21c ti,mux-clock./0123auxclkreq4_ck@220 ti,mux-clock./0123 auxclkreq5_ck@224 ti,mux-clock./0123$clockdomainstarget-module@c000ti,sysc-omap4ti,sysc }revsysc+ vscm@c000ti,omap4-scm-wkupsegment@10000simple-pm-bus+xv@@PPtarget-module@0ti,sysc-omap2ti,sysc}revsyscsyss    fckdbclk+ vgpio@0ti,omap4-gpio ]-?O2target-module@4000ti,sysc-omap2ti,sysc@@@}revsyscsyss"  fck+ v@wdt@0ti,omap4-wdtti,omap3-wdt ]Ptarget-module@8000ti,sysc-omap2-timerti,sysc}revsyscsyss'   fck+ v[otimer@0ti,omap3430-timer fcktimer_sys_ck ]%z  target-module@c000ti,sysc-omap2ti,sysc}revsyscsyss'   Xfck+ vkeypad@0ti,omap4-keypad ]x}mpuf?* !"@%-./kA4:,N0;B9<s&i#$=Cr2j1g>`ltarget-module@e000ti,sysc-omap4ti,sysc }revsysc+ vpinmux@40 ti,omap4-padconfpinctrl-single@8+2 'pinmux_twl6030_wkup_pinsDvsegment@20000simple-pm-bus+v``  00@@PPpptarget-module@0ti,sysc Xdisabled+ vtarget-module@2000ti,sysc Xdisabled+ v target-module@4000ti,sysc Xdisabled+ v@target-module@6000ti,sysc Xdisabled+0v`p 0interconnect@4a000000ti,omap4-l4-cfgsimple-pm-bush4 5fckJJJ }aplaia0+TvJJJJ J (J(0J0segment@0simple-pm-bus+v 00@@PP``pp@  00 ``pp @@PPtarget-module@2000ti,sysc-omap4ti,sysc   }revsysc+ v scm@0ti,omap4-scm-coresimple-bus+ vscm_conf@0syscon+control-phy@300ti,control-phy-usb2}powerfcontrol-phy@33cti,control-phy-otghs<}otghs_controletarget-module@4000ti,sysc-omap4ti,sysc@}rev+ v@cm1@0ti,omap4-cm1simple-bus + v clocks+extalt_clkin_ck fixed-clock_Dpad_clks_src_ck fixed-clock_6pad_clks_ck@108ti,gate-clock6pad_slimbus_core_clks_ck fixed-clock_secure_32k_clk_src_ck fixed-clock_slimbus_src_clk fixed-clock_7slimbus_clk@108ti,gate-clock7 sys_32k_ck fixed-clock_virt_12000000_ck fixed-clock_ virt_13000000_ck fixed-clock_]@ virt_16800000_ck fixed-clock_Yvirt_19200000_ck fixed-clock_$virt_26000000_ck fixed-clock_virt_27000000_ck fixed-clock_virt_38400000_ck fixed-clock_Itie_low_clock_ck fixed-clock_utmi_phy_clkout_ck fixed-clock_xclk60mhsp1_ck fixed-clock_`xclk60mhsp2_ck fixed-clock_axclk60motg_ck fixed-clock_dpll_abe_ck@1e0ti,omap4-dpll-m4xen-clock89:dpll_abe_x2_ck@1f0ti,omap4-dpll-x2-clock:;dpll_abe_m2x2_ck@1f0ti,divider-clock;o<abe_24m_fclkfixed-factor-clock<abe_clk@108ti,divider-clock<dpll_abe_m3x2_ck@1f4ti,divider-clock;o=core_hsd_byp_clk_mux_ck@12c ti,mux-clock=,>dpll_core_ck@120ti,omap4-dpll-core-clock> $,(?dpll_core_x2_ckti,omap4-dpll-x2-clock?@dpll_core_m6x2_ck@140ti,divider-clock@o@dpll_core_m2_ck@130ti,divider-clock?o0Addrphy_ckfixed-factor-clockAdpll_core_m5x2_ck@13cti,divider-clock@o<Bdiv_core_ck@100ti,divider-clockBMdiv_iva_hs_clk@1dcti,divider-clockBFdiv_mpu_hs_clk@19cti,divider-clockBLdpll_core_m4x2_ck@138ti,divider-clock@o8Cdll_clk_div_ckfixed-factor-clockCdpll_abe_m2_ck@1f0ti,divider-clock:Pdpll_core_m3x2_gate_ck@134 ti,composite-no-wait-gate-clock@4Ddpll_core_m3x2_div_ck@134ti,composite-divider-clock@4Edpll_core_m3x2_ckti,composite-clockDEdpll_core_m7x2_ck@144ti,divider-clock@oDiva_hsd_byp_clk_mux_ck@1ac ti,mux-clockFGdpll_iva_ck@1a0ti,omap4-dpll-clockGH7Hdpll_iva_x2_ckti,omap4-dpll-x2-clockHIdpll_iva_m4x2_ck@1b8ti,divider-clockIoJ~Jdpll_iva_m5x2_ck@1bcti,divider-clockIoK] Kdpll_mpu_ck@160ti,omap4-dpll-clockL`dlhdpll_mpu_m2_ck@170ti,divider-clockopper_hs_clk_div_ckfixed-factor-clock=Qusb_hs_clk_div_ckfixed-factor-clock=Wl3_div_ck@100ti,divider-clockMNl4_div_ck@100ti,divider-clockNlp_clk_div_ckfixed-factor-clock<mpu_periphclkfixed-factor-clockocp_abe_iclk@528ti,divider-clock O(per_abe_24m_fclkfixed-factor-clockPdummy_ck fixed-clock_clockdomainsmpuss_cm@300 ti,omap4-cm+ vclk@20 ti,clkctrl tesla_cm@400 ti,omap4-cm+ vclk@20 ti,clkctrl babe_cm@500 ti,omap4-cm+ vclk@20 ti,clkctrl lOtarget-module@8000ti,sysc-omap4ti,sysc}rev+ v cm2@0ti,omap4-cm2simple-bus + v clocks+per_hsd_byp_clk_mux_ck@14c ti,mux-clockQLRdpll_per_ck@140ti,omap4-dpll-clockR@DLHSdpll_per_m2_ck@150ti,divider-clockSP[dpll_per_x2_ck@150ti,omap4-dpll-x2-clockSPTdpll_per_m2x2_ck@150ti,divider-clockToPZdpll_per_m3x2_gate_ck@154 ti,composite-no-wait-gate-clockTTUdpll_per_m3x2_div_ck@154ti,composite-divider-clockTTVdpll_per_m3x2_ckti,composite-clockUVdpll_per_m4x2_ck@158ti,divider-clockToXdpll_per_m5x2_ck@15cti,divider-clockTo\dpll_per_m6x2_ck@160ti,divider-clockTo`Ydpll_per_m7x2_ck@164ti,divider-clockToddpll_usb_ck@180ti,omap4-dpll-j-type-clockWXdpll_usb_clkdcoldo_ck@1b4ti,fixed-factor-clockXodpll_usb_m2_ck@190ti,divider-clockXo\ducati_clk_mux_ck@100 ti,mux-clockMYfunc_12m_fclkfixed-factor-clockZfunc_24m_clkfixed-factor-clock[func_24mc_fclkfixed-factor-clockZfunc_48m_fclk@108ti,divider-clockZfunc_48mc_fclkfixed-factor-clockZfunc_64m_fclk@108ti,divider-clockfunc_96m_fclk@108ti,divider-clockZinit_60m_fclk@104ti,divider-clock\_per_abe_nc_fclk@108ti,divider-clockPusb_phy_cm_clk32k@640ti,gate-clock@gclockdomainsl3_init_clkdmti,clockdomainXl4_ao_cm@600 ti,omap4-cm+ vclk@20 ti,clkctrl il3_1_cm@700 ti,omap4-cm+ vclk@20 ti,clkctrl l3_2_cm@800 ti,omap4-cm+ vclk@20 ti,clkctrl ducati_cm@900 ti,omap4-cm + v clk@20 ti,clkctrl l3_dma_cm@a00 ti,omap4-cm + v clk@20 ti,clkctrl ]l3_emif_cm@b00 ti,omap4-cm + v clk@20 ti,clkctrl d2d_cm@c00 ti,omap4-cm + v clk@20 ti,clkctrl hl4_cfg_cm@d00 ti,omap4-cm + v clk@20 ti,clkctrl 5l3_instr_cm@e00 ti,omap4-cm+ vclk@20 ti,clkctrl $ ivahd_cm@f00 ti,omap4-cm+ vclk@20 ti,clkctrl iss_cm@1000 ti,omap4-cm+ vclk@20 ti,clkctrl ml3_dss_cm@1100 ti,omap4-cm+ vclk@20 ti,clkctrl l3_gfx_cm@1200 ti,omap4-cm+ vclk@20 ti,clkctrl l3_init_cm@1300 ti,omap4-cm+ vclk@20 ti,clkctrl ^l4_per_cm@1400 ti,omap4-cm+ vclock@20ti,clkctrl-l4-perti,clkctrl Dnclock@1a0 ti,clkctrl-l4-secureti,clkctrl<~target-module@56000ti,sysc-omap2ti,sysc``,`(}revsyscsyss#    ]fck+ v`dma-controller@0ti,omap4430-sdmati,omap-sdma0]   target-module@58000ti,sysc-omap2ti,sysc}revsyscsyss#  ^fck+ vPhsi@0 ti,omap4-hsi@P}sysgdd ^hsi_fck ]Ggdd_mpu+ v@hsi-port@2000ti,omap4-hsi-port (}txrx ]Chsi-port@3000ti,omap4-hsi-port08}txrx ]Dtarget-module@5e000ti,sysc Xdisabled+ v target-module@62000ti,sysc-omap2ti,sysc   }revsyscsyss  ^Hfck+ v usbhstll@0 ti,usbhs-tll ]Ntarget-module@64000ti,sysc-omap4ti,sysc@@@}revsyscsyss ^8fck+ v@usbhshost@0ti,usbhs-host+ v _`a3refclk_60m_intrefclk_60m_ext_p1refclk_60m_ext_p2ohci@800ti,ohci-omap3 ]L!ehci@c00 ti,ehci-omap  ]Mtarget-module@66000ti,sysc-omap2ti,sysc```}revsyscsyss  bfckhc9c@rstctrl+ v`mmu@0ti,omap4-iommu ]Lsegment@80000simple-pm-bus+v      @@PP``pp` `p p        target-module@29000ti,sysc Xdisabled+ vtarget-module@2b000ti,sysc-omap2ti,sysc}revsyscsyss   ^@fck+ vusb_otg_hs@0ti,omap4-musb]\]mcdmaYdad fusb2-phyp{ e2target-module@2d000ti,sysc-omap2ti,sysc}revsyscsyss   ^fck+ vocp2scp@0ti,omap-ocp2scp+ vusb2phy@80 ti,omap-usb2Xfgwkupclkdtarget-module@36000ti,sysc-omap2ti,sysc```}revsyscsyss  hfck+ v`target-module@4d000ti,sysc-omap2ti,sysc}revsyscsyss  hfck+ vtarget-module@59000ti,sysc-omap4-srti,sysc8}sysc ifck+ vsmartreflex@0ti,omap4-smartreflex-mpu ]target-module@5b000ti,sysc-omap4-srti,sysc8}sysc ifck+ vsmartreflex@0ti,omap4-smartreflex-iva ]ftarget-module@5d000ti,sysc-omap4-srti,sysc8}sysc ifck+ vsmartreflex@0ti,omap4-smartreflex-core ]target-module@60000ti,sysc Xdisabled+ vtarget-module@74000ti,sysc-omap4ti,sysc@@ }revsysc  5fck+ v@mailbox@0ti,omap4-mailbox ]mbox-ipu  mbox-dsp  target-module@76000ti,sysc-omap2ti,sysc```}revsyscsyss   5fck+ v`spinlock@0ti,omap4-hwspinlocksegment@100000simple-pm-bus+`v  00target-module@0ti,sysc-omap4ti,sysc }revsysc+ vpinmux@40 ti,omap4-padconfpinctrl-single@+2 'defaultjkopinmux_mcpdm_pins(Dpinmux_uart2_pins Drpinmux_uart3_pins Dppinmux_uart4_pinsDspinmux_twl6040_pinsD`xpinmux_dmic_pins Dpinmux_mcbsp1_pins Dpinmux_mcbsp2_pins Dpinmux_mcspi1_pins Dpinmux_dss_hdmi_pinsDZ\^jpinmux_tpd12s015_pinsD"HX kpinmux_i2c1_pinsDtpinmux_i2c2_pinsD}pinmux_i2c3_pinsDqpinmux_i2c4_pinsDpinmux_wl12xx_gpioD<pinmux_wl12xx_pins8D:  pinmux_enet_enable_gpioD0 pinmux_ks8851_pinsDpinmux_twl6030_pinsD^Auomap4_padconf_global@5a0sysconsimple-busp+ vplpbias_regulator@60ti,pbias-omap4ti,pbias-omap`)lpbias_mmc_omap40pbias_mmc_omap4?w@W-target-module@2000ti,sysc Xdisabled+ v target-module@8000ti,sysc Xdisabled+ vtarget-module@a000ti,sysc-omap4ti,sysc }revsysc  o mfck+ vsegment@180000simple-pm-bus+segment@200000simple-pm-bus+hv!!  @ @P P` `p p ! 0!0  !!`!`p!p@!@P!P!!""`"`p"p""""!!target-module@4000ti,sysc Xdisabled+ v@target-module@6000ti,sysc Xdisabled+ v`target-module@a000ti,sysc Xdisabled+ vtarget-module@c000ti,sysc Xdisabled+ vtarget-module@10000ti,sysc Xdisabled+ vtarget-module@12000ti,sysc Xdisabled+ v target-module@14000ti,sysc Xdisabled+ v@target-module@16000ti,sysc Xdisabled+ v`target-module@18000ti,sysc Xdisabled+ vtarget-module@1c000ti,sysc Xdisabled+ vtarget-module@1e000ti,sysc Xdisabled+ vtarget-module@20000ti,sysc Xdisabled+ vtarget-module@26000ti,sysc Xdisabled+ v`target-module@28000ti,sysc Xdisabled+ vtarget-module@2a000ti,sysc Xdisabled+ vsegment@280000simple-pm-bus+segment@300000simple-pm-bus+v042@@2@ `2`p2p2232 2@target-module@0ti,sysc Xdisabled+xv@@@ ``pp @interconnect@48000000ti,omap4-l4-persimple-pm-bush nfck0HHHHHH}aplaia0ia1ia2ia3+vH H segment@0simple-pm-bus+v  00@@PP``ppPP``pp  00 ` ` p p``pp``pp             @ @ ` ` @     0 0 @ @ P P        P P ` `  0 0 P Ptarget-module@20000ti,sysc-omap2ti,syscPTX}revsyscsyss  n0fck+ vserial@0ti,omap4-uart ]J_lJodefaultptarget-module@32000ti,sysc-omap2-timerti,sysc   }revsyscsyss'   nfck+ v timer@0ti,omap3430-timernfcktimer_sys_ck ]&target-module@34000ti,sysc-omap4-timerti,sysc@@ }revsysc n fck+ v@timer@0ti,omap4430-timern fcktimer_sys_ck ]'target-module@36000ti,sysc-omap4-timerti,sysc`` }revsysc n(fck+ v`timer@0ti,omap4430-timern(fcktimer_sys_ck ](target-module@3e000ti,sysc-omap4-timerti,sysc }revsysc n0fck+ vtimer@0ti,omap4430-timern0fcktimer_sys_ck ]-target-module@40000ti,sysc Xdisabled+ vtarget-module@55000ti,sysc-omap2ti,syscPPQ}revsyscsyss n@n@ fckdbclk+ vPgpio@0ti,omap4-gpio ]?O2target-module@57000ti,sysc-omap2ti,syscppq}revsyscsyss nHnH fckdbclk+ vpgpio@0ti,omap4-gpio ]?O2target-module@59000ti,sysc-omap2ti,sysc}revsyscsyss nPnP fckdbclk+ vgpio@0ti,omap4-gpio ] ?O2ytarget-module@5b000ti,sysc-omap2ti,sysc}revsyscsyss nXnX fckdbclk+ vgpio@0ti,omap4-gpio ]!?O2target-module@5d000ti,sysc-omap2ti,sysc}revsyscsyss n`n` fckdbclk+ vgpio@0ti,omap4-gpio ]"?O2target-module@60000ti,sysc-omap2ti,sysc}revsyscsyss  nfck+ vi2c@0 ti,omap4-i2c ]=+defaultq_tmp105@48 ti,tmp105Hbh1780@29 rohm,bh1780)target-module@6a000ti,sysc-omap2ti,syscPTX}revsyscsyss  n fck+ vserial@0ti,omap4-uart ]H_ltarget-module@6c000ti,sysc-omap2ti,syscPTX}revsyscsyss  n(fck+ vserial@0ti,omap4-uart ]I_lIodefaultrtarget-module@6e000ti,sysc-omap2ti,syscPTX}revsyscsyss  n8fck+ vserial@0ti,omap4-uart ]F_lFodefaultstarget-module@70000ti,sysc-omap2ti,sysc}revsyscsyss  nfck+ vi2c@0 ti,omap4-i2c ]8+defaultt_twl@48H ] ti,twl60302defaultuvrtcti,twl4030-rtc] regulator-vaux1ti,twl6030-vaux1?B@W-regulator-vaux2ti,twl6030-vaux2?OW*regulator-vaux3ti,twl6030-vaux3?B@W-regulator-vmmcti,twl6030-vmmc?OW-regulator-vppti,twl6030-vpp?w@W&%regulator-vusimti,twl6030-vusim?OW,@ regulator-vdacti,twl6030-vdacregulator-vanati,twl6030-vanaregulator-vcxioti,twl6030-vcxioregulator-vusbti,twl6030-vusbwregulator-v1v8ti,twl6030-v1v8zregulator-v2v1ti,twl6030-v2v1{usb-comparatorti,twl6030-usb] wpwmti,twl6030-pwmpwmledti,twl6030-pwmledgpadcti,twl6030-gpadc]twl@4b ti,twl6040Kdefaultx ]w yz{|'|vibra6ET e target-module@72000ti,sysc-omap2ti,sysc   }revsyscsyss  nfck+ v i2c@0 ti,omap4-i2c ]9+default}_target-module@76000ti,sysc-omap4ti,sysc`` }revsysc nfck+ v`target-module@78000ti,sysc-omap2ti,sysc}revsyscsyss   n8fck+ velm@0ti,am3352-elm  ] Xdisabledtarget-module@86000ti,sysc-omap2-timerti,sysc```}revsyscsyss'   nfck+ v`timer@0ti,omap3430-timernfcktimer_sys_ck ].target-module@88000ti,sysc-omap4-timerti,sysc }revsysc nfck+ vtimer@0ti,omap4430-timernfcktimer_sys_ck ]/target-module@90000ti,sysc-omap2ti,sysc   }revsysc ~ fck+ v rng@0 ti,omap4-rng  ]4target-module@96000ti,sysc-omap2ti,sysc `}sysc  nfck+ v `mcbsp@0ti,omap4-mcbsp}mpu ]commonv txrx Xdisabledtarget-module@98000ti,sysc-omap4ti,sysc   }revsysc nfck+ v spi@0ti,omap4-mcspi ]A+@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3defaulteth@0defaultks8851n6 ]  target-module@9a000ti,sysc-omap4ti,sysc   }revsysc nfck+ v spi@0ti,omap4-mcspi ]B+ +,-.tx0rx0tx1rx1target-module@9c000ti,sysc-omap4ti,sysc   }revsysc ^fck+ v mmc@0ti,omap4-hsmmc ]S=>txrxtarget-module@9e000ti,sysc Xdisabled+ v target-module@a2000ti,sysc Xdisabled+ v target-module@a4000ti,sysc Xdisabled+v @ Ptarget-module@a5000ti,sysc-omap2ti,sysc P0 P4 P8}revsyscsyss  ~fck+ v Pdes@0 ti,omap4-des ]Ruttxrxtarget-module@a8000ti,sysc Xdisabled+ v @target-module@ad000ti,sysc-omap4ti,sysc   }revsysc nfck+ v mmc@0ti,omap4-hsmmc ]^MNtxrx Xdisabledtarget-module@b0000ti,sysc Xdisabled+ v target-module@b2000ti,sysc-omap2ti,sysc   }revsyscsyss [ nhfck+ v 1w@0 ti,omap3-1w ]:target-module@b4000ti,sysc-omap4ti,sysc @ @ }revsysc ^fck+ v @mmc@0ti,omap4-hsmmc ]V/0txrxtarget-module@b8000ti,sysc-omap4ti,sysc   }revsysc nfck+ v spi@0ti,omap4-mcspi ][+tx0rx0target-module@ba000ti,sysc-omap4ti,sysc   }revsysc nfck+ v spi@0ti,omap4-mcspi ]0+FGtx0rx0target-module@d1000ti,sysc-omap4ti,sysc   }revsysc nfck+ v mmc@0ti,omap4-hsmmc ]`9:txrx Xdisabledtarget-module@d5000ti,sysc-omap4ti,sysc P P }revsysc n@fck+ v Pmmc@0ti,omap4-hsmmc ];;<txrxdefault#+wlcore@2 ti,wl1281 ]6Jsegment@200000simple-pm-bus+v55target-module@150000ti,sysc-omap2ti,sysc}revsyscsyss  nfck+ vi2c@0 ti,omap4-i2c ]>+default_hmc5843@1ehoneywell,hmc5843target-module@48210000ti,sysc-omap4-simpleti,sysch fck+ vH!mpu ti,omap4-mpu_interconnect@40100000ti,omap4-l4-abesimple-pm-bus@@}laaph+v@IIsegment@0simple-pm-bus+0v  00@@PP``pp  00      IIIII I I0I0I@I@IPIPI`I`IpIpIIIIIIIIIIIIIIIII I I0I0IIIIIIIIIIIIIIIIIIIII I I I I I I I III I target-module@22000ti,sysc-omap2ti,sysc }sysc  O(fck+v I I mcbsp@0ti,omap4-mcbspI }mpudma ]commonv!"txrxXokaydefaulttarget-module@24000ti,sysc-omap2ti,sysc@}sysc  O0fck+v@I@I@mcbsp@0ti,omap4-mcbspI@}mpudma ]commonvtxrxXokaydefaulttarget-module@26000ti,sysc-omap2ti,sysc`}sysc  O8fck+v`I`I`mcbsp@0ti,omap4-mcbspI`}mpudma ]commonvtxrx Xdisabledtarget-module@28000ti,sysc-mcaspti,sysc }revsysc O fck+vIItarget-module@2a000ti,sysc Xdisabled+vIItarget-module@2e000ti,sysc-omap4ti,sysc }revsysc Ofck+vIIdmic@0ti,omap4-dmicI}mpudma ]rCup_linkXokaydefaulttarget-module@30000ti,sysc-omap2ti,sysc}revsyscsyss"  Ohfck+vIIwdt@0ti,omap4-wdtti,omap3-wdt ]Ptarget-module@32000ti,sysc-omap4ti,sysc   }revsysc Ofck+v I I Xokaydefaultmcpdm@0ti,omap4-mcpdmI }mpudma ]pABup_linkdn_linkpdmclktarget-module@38000ti,sysc-omap4-timerti,sysc }revsysc OHfck+vIItimer@0ti,omap4430-timerIOHfcktimer_sys_ck ])dtarget-module@3a000ti,sysc-omap4-timerti,sysc }revsysc OPfck+vIItimer@0ti,omap4430-timerIOPfcktimer_sys_ck ]*dtarget-module@3c000ti,sysc-omap4-timerti,sysc }revsysc OXfck+vIItimer@0ti,omap4430-timerIOXfcktimer_sys_ck ]+dtarget-module@3e000ti,sysc-omap4-timerti,sysc }revsysc O`fck+vIItimer@0ti,omap4430-timerIO`fcktimer_sys_ck ],dtarget-module@80000ti,sysc Xdisabled+vIItarget-module@a0000ti,sysc Xdisabled+v I I target-module@c0000ti,sysc Xdisabled+v I I target-module@f1000ti,sysc-omap4ti,sysc }revsysc  Ofck+vIItarget-module@50000000ti,sysc-omap2ti,syscPPP}revsyscsyss  q fck+vPP@gpmc@50000000ti,omap4430-gpmcP+ ]rxtxNfck2?Otarget-module@52000000ti,sysc-omap4ti,syscRR }revsyscoh mfck+ vRtarget-module@54000000ti,sysc-omap4-simpleti,sysch fck+ vTpmuarm,cortex-a9-pmutarget-module@55082000ti,sysc-omap2ti,syscU U U }revsyscsyss  fck94@rstctrl vU +mmu@0ti,omap4-iommu ]dLtarget-module@4012c000ti,sysc-omap4ti,sysc@@ }revsysc O@fck+v@IItarget-module@4e000000ti,sysc-omap2ti,syscNN }revsysc  vN+dmm@0 ti,omap4-dmm ]qtarget-module@4c000000ti,sysc-omap4-simpleti,syscL}rev fcko+ vLemif@0 ti,emif-4d ]n target-module@4d000000ti,sysc-omap4-simpleti,syscM}rev fcko+ vMemif@0 ti,emif-4d ]o dsp ti,omap4-dsp "9c b)omap4-dsp-fw.xe64T7 Xdisabledipu@55020000 ti,omap4-ipuU}l2ram"944 )omap4-ipu-fw.xem37 Xdisabledtarget-module@4b501000ti,sysc-omap2ti,syscKPKPKP}revsyscsyss  ~fck+ vKPaes@0 ti,omap4-aes ]Uontxrxtarget-module@4b701000ti,sysc-omap2ti,syscKpKpKp}revsyscsyss  ~fck+ vKpaes@0 ti,omap4-aes ]@rqtxrxtarget-module@4b100000ti,sysc-omap3-shamti,syscKKK}revsyscsyss   ~(fck+ vKsham@0ti,omap4-sham ]3wrxregulator-abb-mpu ti,abb-v20abb_mpu+>W2hXokayJ0{J0`}base-addressint-addressxxO1regulator-abb-iva ti,abb-v20abb_iva+>W2h XdisabledJ0{J0`}base-addressint-addresstarget-module@56000000ti,sysc-omap4ti,syscVV }revsysch fck+ vVOtarget-module@58000000ti,sysc-omap2ti,syscXX }revsyss h0 fckhdmi_clksys_clktv_clk+ vXdss@0 ti,omap4-dssXokay fck+ vtarget-module@1000ti,sysc-omap2ti,sysc}revsyscsyss     fcksys_clk+ vdispc@0ti,omap4-dispc ] fcktarget-module@2000ti,sysc-omap2ti,sysc   }revsyscsyss    fcksys_clk+ v encoder@0 XdisabledNfckicktarget-module@3000ti,sysc-omap2ti,sysc0}rev sys_clk+ v0encoder@0ti,omap4-venc Xdisabled fcktarget-module@4000ti,sysc-omap2ti,sysc@@@}revsyscsyss  + v@encoder@0 ti,omap4-dsi@ }protophypll ]5Xokay  fcksys_clk+portendpointpanel@0tpo,taalpanel-dsi-cmlcd0 yportendpointtarget-module@5000ti,sysc-omap2ti,syscPPP}revsyscsyss  + vPencoder@0 ti,omap4-dsi@ }protophypll ]TXokay  fcksys_clk+portendpointpanel@0tpo,taalpanel-dsi-cmlcd1 yportendpointtarget-module@6000ti,sysc-omap4ti,sysc`` }revsysc  fckdss_clk+ v` encoder@0ti,omap4-hdmi }wppllphycore ]eXokay  fcksys_clkL audio_txportendpointtarget-module@5a000000ti,sysc-omap4ti,syscZZ }revsysc  h9@rstctrl fck+vZZ[[iva ti,ivahdbandgap@4a002260J"`J#,ti,omap4430-bandgap thermal-zonescpu_thermalN tripscpu_alert  passivecpu_crit H  criticalcooling-mapsmap0  lpddr2#Elpida,ECB240ABACNjedec,lpddr2-s4 . 6  ? M Z f v      lpddr2-timings@0jedec,lpddr2-timings  ׄ R FP :  ' L L L : | !P &_ ,~@ 2B@ :p Fplpddr2-timings@1jedec,lpddr2-timings   R FP :  ' ' L L : | !P &_ ,~@ 2B@ :p Fpmemory@80000000memoryЀ@fixedregulator-vdd-ethdefaultregulator-fixed0VDD_ETH?2ZW2Z  Y kafixedregulator-vbatregulator-fixed0VBAT?98pW98p Y|led-controller-1 gpio-ledsled-1omap4:green:debug0 led-2omap4:green:debug1 led-3omap4:green:debug2 led-4omap4:green:debug3 led-5omap4:green:debug4 led-6omap4:blue:user  led-7omap4:red:user  led-8omap4:green:user  led-controller-2 pwm-ledsled-9omap4::keypad |w5 led-10omap4:green:chrg |w5 backlightpwm-backlight |w58 (2<FPZdnx soundti,abe-twl6040 SDP4430  I   { Headset StereophoneHSOLHeadset StereophoneHSOREarphone SpkEPExt SpkHFLExt SpkHFRLine OutAUXLLine OutAUXRVibratorVIBRALVibratorVIBRARHSMICHeadset MicHeadset MicHeadset Mic BiasMAINMICMain Handset MicMain Handset MicMain Mic BiasSUBMICSub Handset MicSub Handset MicMain Mic BiasAFMLLine InAFMRLine InDMicDigital MicDigital MicDigital Mic1 Biaswl12xx_vmmcdefaultregulator-fixed0vwl1271?w@Ww@  kpencoder ti,tpd12s015$ ports+port@0endpointport@1endpointconnectorhdmi-connectorhdmicportendpoint compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3mmc0mmc1mmc2mmc3mmc4serial0serial1serial2serial3rproc0rproc1display0display1display2device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-points#cooling-cellsphandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptspower-domainsrangesreg-namesti,sysc-sidle#clock-cellsti,index-starts-at-oneti,bit-shiftclock-multclock-divti,max-divti,dividers#power-domain-cells#reset-cellsti,sysc-maskti,syss-maskti,gpio-always-ongpio-controller#gpio-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentskeypad,num-rowskeypad,num-columnslinux,keymaplinux,input-no-autorepeat#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsstatusclock-frequencyti,autoidle-shiftti,invert-autoidle-bitti,index-power-of-twoassigned-clock-ratesti,clock-divti,clock-multti,sysc-midle#dma-cellsdma-channelsdma-requestsinterrupt-namesremote-wakeup-connectedresetsreset-names#iommu-cellsusb-phyphysphy-namesmultipointnum-epsram-bitsctrl-moduleinterface-typemodepower#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rx#hwlock-cellspinctrl-namespinctrl-0sysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,sysc-delay-usinterrupts-extendedti,timer-pwmregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highvddvibl-supplyvddvibr-supplyti,vibldrv-resti,vibrdrv-resti,viblmotor-resti,vibrmotor-resti,buffer-sizedmasdma-namesti,spi-num-csspi-max-frequencyvdd-supplyreset-gpiosti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthti,non-removablecap-power-off-cardref-clock-frequencytcxo-clock-frequencysramti,timer-dspti,no-idle-on-initgpmc,num-csgpmc,num-waitpinsti,iommu-bus-err-backphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertcs1-useddevice-handleti,bootregiommusfirmware-namemboxesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_inforemote-endpointlaneslabelvdda-supply#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresistripcooling-devicedensityio-widthtRPab-min-tcktRCD-min-tcktWR-min-tcktRASmin-min-tcktRRD-min-tcktWTR-min-tcktXP-min-tcktRTP-min-tcktCKE-min-tcktCKESR-min-tcktFAW-min-tckmin-freqmax-freqtRPabtRCDtWRtRAS-mintRRDtWTRtXPtRTPtCKESRtDQSCK-maxtFAWtZQCStZQCLtZQinittRAS-max-nstDQSCK-max-deratedregulator-boot-onstartup-delay-uspwmsmax-brightnessbrightness-levelsdefault-brightness-levelti,modelti,jack-detectionti,mclk-freqti,mcpdmti,dmicti,twl6040ti,audio-routing