� ���P8��(��|$mediatek,mt8195-evbmediatek,mt8195 +!7MediaTek MT8195 evaluation boardaliases=/soc/mailbox@10320000B/soc/mailbox@10330000G/soc/serial@11001100cpus+cpu@0Ocpuarm,cortex-a55[_pscim�ec3@�4���� cpu@100Ocpuarm,cortex-a55[_pscim�ec3@�4���� cpu@200Ocpuarm,cortex-a55[_pscim�ec3@�4���� cpu@300Ocpuarm,cortex-a55[_pscim�ec3@�4���� cpu@400Ocpuarm,cortex-a78[_pscim��f������� cpu@500Ocpuarm,cortex-a78[_pscim��f�������cpu@600Ocpuarm,cortex-a78[_pscim��f�������cpu@700Ocpuarm,cortex-a78[_pscim��f�������cpu-mapcluster0core0� core1� core2� core3� core4� core5�core6�core7�idle-states�pscicpu-off-larm,idle-state�2&_6D�cpu-off-barm,idle-state�-&�6��cluster-off-larm,idle-state�7&�6H�cluster-off-barm,idle-state�2&�6��l2-cache0cache��l2-cache1cache��l3-cachecache�dsu-pmu arm,dsu-pmuG R dmic-codec dmic-codecWd2mt8195-soundt �disabledfixed-factor-clock-13mfixed-factor-clock�����clk13m�&oscillator-26m fixed-clock������clk26m�oscillator-32k fixed-clock����clk32kperformance-controller@11bc10mediatek,cpufreq-hw [� �0 ��pmu-a55arm,cortex-a55-pmu Gpmu-a78arm,cortex-a78-pmu Gpsci arm,psci-1.0fsmctimerarm,armv8-timer @G   soc+ simple-bus�interrupt-controller@c000000 arm,gic-v3��  [   G �ppi-partitionsinterrupt-partition-0' �interrupt-partition-1' �syscon@10000000 mediatek,mt8195-topckgensyscon[��syscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfd[�0�syscon@10003000mediatek,mt8195-pericfgsyscon[0��/pinctrl@10005000mediatek,mt8195-pinctrl�[P�������B=iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintGWc�G���i2c0-pins�7pinso ve��i2c1-pins�8pinso  ve��i2c4-pins�9pinsove�i2c6-pins�5pinsovei2c7-pinspinsovenor-pins�3pins0 o����pins1 o���vuart0-pins�,pinsobcsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd[`power-controller!mediatek,mt8195-power-controller+��(power-domain@8[+�power-domain@9[ ��mfg�+�power-domain@10[ �power-domain@11[ �power-domain@12[ �power-domain@13[ �power-domain@14[�power-domain@15[�� @AK�   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�ether�power-domain@6[�Xn �adspadsp1+��power-domain@7[ �g"n2�audioaudio1audio2audio3��watchdog@10007000mediatek,mt8195-wdt�[p0�+syscon@1000c000"mediatek,mt8195-apmixedsyssyscon[���timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer[pG �&pwrap@10024000mediatek,mt8195-pwrapsyscon[@=pwrapG�� �spiwrap$�spmi@10027000mediatek,mt8195-spmi [p� =pmifspmimst�E(�pmif_sys_ckpmif_tmr_ckspmimst_clk_mux$�infra-iommu@10315000mediatek,mt8195-iommu-infra[1PPPG.mailbox@10320000mediatek,mt8195-gce[2@G�;��_mailbox@10330000mediatek,mt8195-gce[3@G�;�scp@10500000mediatek,mt8195-scp0[Prp�=sramcfgl1tcmG� �disabledclock-controller@10720000mediatek,mt8195-scp_adsp[r��'dsp@10803000mediatek,mt8195-dsp [�0� =cfgsram,�Xn�'#K�adsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_hG(Urxtx`)* �disabledmailbox@10816000mediatek,mt8195-adsp-mbox;[�`G��)mailbox@10817000mediatek,mt8195-adsp-mbox;[�pG��*mt8195-afe-pcm@10890000mediatek,mt8195-audio[�gG(G6y+ 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compatibleinterrupt-parent#address-cells#size-cellsmodelgce0gce1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptscpusnum-channelswakeup-delay-msmediatek,platformstatus#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-upmediatek,drive-strength-advdrive-strengthbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellspower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0#io-channel-cellsphysmediatek,syscon-wakeupwakeup-sourceusb2-lpm-disablespi-max-frequencybits#phy-cellsnvmem-cellsnvmem-cell-namesmediatek,smimediatek,larb-idmediatek,larbsiommusmediatek,gce-client-regmediatek,gce-eventsstdout-path