� ��؅8θ( �΀%pine64,pinephone-prorockchip,rk3399 +7Pine64 PinePhonePro=handsetaliasesJ/ethernet@fe300000T/i2c@ff3c0000Y/i2c@ff110000^/i2c@ff120000c/i2c@ff130000h/i2c@ff3d0000m/i2c@ff140000r/i2c@ff150000w/i2c@ff160000|/i2c@ff3e0000�/serial@ff180000�/serial@ff190000�/serial@ff1a0000�/serial@ff1b0000�/serial@ff370000�/mmc@fe310000�/mmc@fe320000�/mmc@fe330000cpus+cpu-mapcluster0core0�core1�core2�core3�cluster1core0�core1�cpu@0�cpuarm,cortex-a53��psci����d - A Lcpu@1�cpuarm,cortex-a53��psci����d - A Lcpu@2�cpuarm,cortex-a53��psci����d - A Lcpu@3�cpuarm,cortex-a53��psci����d - A Lcpu@100�cpuarm,cortex-a72��psci�� �� - ALthermal-idle�T'`�cpu@101�cpuarm,cortex-a72��psci�� �� - ALthermal-idle�T'`�idle-statesppscicpu-sleeparm,idle-state}��x`���L cluster-sleeparm,idle-state}���`���L display-subsystemrockchip,display-subsystem�memory-controllerrockchip,rk3399-dmc�����dmc_clk �disabledpmu_a53arm,cortex-a53-pmu�pmu_a72arm,cortex-a72-pmu�psci arm,psci-1.0�smctimerarm,armv8-timer@�   xin24m fixed-clockn6.xin24mALpcie@f8000000rockchip,rk3399-pcie ���Naxi-baseapb-base�pci+Xiu ���G��aclkaclk-perfhclkpm0�123syslegacyclient�`��� �,�pcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38ւ��������8��������(�coremgmtmgmt-stickypipepmpclkaclk �disabledinterrupt-controller�XLethernet@fe300000rockchip,rk3399-gmac��0� macirq8�ighfj�fM�stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac�� �stmmaceth  �disabledmmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc��1@�@+�р ��M���biuciuciu-driveciu-sample9�y�reset �disabledmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc��2@�A+�рD�T �� ��L���biuciuciu-driveciu-sample9�z�reset�okayis ���default��� mmc@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.1��3� �DNT ���N��clk_xinclk_ahb.emmc_cardclockA�! �phy_arasan��okayi��L�usb@fe380000 generic-ehci��8����"�#�usb �disabledusb@fe3a0000 generic-ohci��:����"�#�usb �disabledusb@fe3c0000 generic-ehci��<����$�%�usb �disabledusb@fe3e0000 generic-ohci��>� ���$�%�usb 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�disabledserial@ff1a0000&rockchip,rk3399-uartsnps,dw-apb-uart���Sb�baudclkapb_pclk�d �default�6�okayserial@ff1b0000&rockchip,rk3399-uartsnps,dw-apb-uart���Tc�baudclkapb_pclk�e �default�7 �disabledspi@ff1c0000(rockchip,rk3399-spirockchip,rk3066-spi���G[�spiclkapb_pclk�D 8 8 %txrx�default�9:;<+ �disabledspi@ff1d0000(rockchip,rk3399-spirockchip,rk3066-spi���H\�spiclkapb_pclk�5 8 8 %txrx�default�=>?@+ �disabledspi@ff1e0000(rockchip,rk3399-spirockchip,rk3066-spi���I]�spiclkapb_pclk�4 88%txrx�default�ABCD+ �disabledspi@ff1f0000(rockchip,rk3399-spirockchip,rk3066-spi���J^�spiclkapb_pclk�C 88%txrx�default�EFGH+ �disabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spi�� �K_�spiclkapb_pclk�� II %txrx�default�JKLM+ �disabledthermal-zonescpu-thermal/dE�SNtripscpu_alert0c��o�EpassiveLOcpu_alert1c �o�EpassiveLPcpu_critcso� Ecriticalcooling-mapsmap0zO����������������map1zPH������������������������������������������������gpu-thermal/dE�SNtripsgpu_alert0c$�o�EpassiveLQgpu_critcso� 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compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4mmc0mmc1mmc2cpudevice_typeregenable-methodcapacity-dmips-mhzclocks#cooling-cellsdynamic-power-coefficientcpu-idle-statesoperating-points-v2cpu-supplyphandleduration-usexit-latency-usentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usmin-residency-usportsrockchip,pmudevfreq-eventsclock-namesstatusinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-mapmax-link-speedmsi-mapphysphy-namesrangesresetsreset-namesinterrupt-controllerpower-domainsrockchip,grfsnps,txpblmax-frequencyfifo-depthassigned-clocksassigned-clock-ratesbus-widthcap-sd-highspeedcd-gpiosdisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplyarasan,soc-ctl-syscondisable-cqe-dcmdmmc-hs200-1_8vnon-removabledr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controller#msi-cellsaffinity#io-channel-cellsreg-shiftreg-io-widthdmasdma-namespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#power-domain-cellspm_qospmu1830-supplyi2c-scl-rising-time-nsi2c-scl-falling-time-nsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendfcs,suspend-voltage-selector#pwm-cellsiommus#iommu-cells#dma-cellsarm,pl330-periph-burst#reset-cellsbt656-supplyaudio-supplysdmmc-supplygpio1830-supply#phy-cellsdrive-impedance-ohmrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daigpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsstdout-pathdebounce-intervallabellinux,codevin-supplyenable-active-highgpio