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mediatek,mt8195-topckgensyscon��syscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfd��]syscon@10003000mediatek,mt8195-pericfgsyscon�0�3pinctrl@10005000mediatek,mt8195-pinctrl��P�������Bjiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintt���?t���default�>�I2S_SPKR_MCLKI2S_SPKR_DATAINI2S_SPKR_LRCKI2S_SPKR_BCLKEC_AP_INT_ODLAP_FLASH_WP_LTCHPAD_INT_ODLEDP_HPD_1V8AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_I2C_TCHPAD_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_AUD_SDAAP_I2C_AUD_SCLAP_I2C_TPM_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHSCR_SCL_1V8EC_AP_HPD_ODPCIE_NVME_RST_LPCIE_NVME_CLKREQ_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLPCIE_WAKE_1V8_ODLCLK_24M_CAM0CAM1_SEN_ENAP_I2C_PWR_SCL_1V8AP_I2C_PWR_SDA_1V8AP_I2C_MISC_SCLAP_I2C_MISC_SDAEN_PP5000_HDMI_XAP_HDMITX_HTPLGAP_HDMITX_SCL_1V8AP_HDMITX_SDA_1V8AP_RTC_CLK32KAP_EC_WATCHDOG_LSRCLKENA0SRCLKENA1PWRAP_SPI0_CS_LPWRAP_SPI0_CKPWRAP_SPI0_MOSIPWRAP_SPI0_MISOSPMI_SCLSPMI_SDAI2S_HP_DATAINI2S_HP_MCLKI2S_HP_BCKI2S_HP_LRCKI2S_HP_DATAOUTSD_CD_ODLEN_PP3300_DISP_XTCHSCR_RST_1V8_LTCHSCR_REPORT_DISABLEEN_PP3300_WLAN_XBT_KILL_1V8_LI2S_SPKR_DATAOUTWIFI_KILL_1V8_LBEEP_ONSCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1AUD_DAT_MISO2SCP_VREQ_VAOAP_SPI_GSC_TPM_CLKAP_SPI_GSC_TPM_MOSIAP_SPI_GSC_TPM_CS_LAP_SPI_GSC_TPM_MISOEN_PP1000_CAM_XAP_EDP_BKLTENUSB3_HUB_RST_LWLAN_ALERT_ODLEC_IN_RW_ODLGSC_AP_INT_ODLHP_INT_ODLCAM0_RST_LCAM1_RST_LTCHSCR_INT_1V8_LCAM1_DET_LRST_ALC1011_LBL_PWM_1V8UART_AP_TX_DBG_RXUART_DBG_TX_AP_RXEN_SPKRAP_EC_WARM_RST_REQUART_SCP_TX_DBGCON_RXUART_DBGCON_TX_SCP_RXKPCOL0MT6315_GPU_INTMT6315_PROC_BC_INTSD_CMDSD_CLKSD_DAT0SD_DAT1SD_DAT2SD_DAT3EMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RSTBEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLMT6360_INT_ODLSCP_JTAG0_TRSTNAP_SPI_EC_CS_LAP_SPI_EC_CLKAP_SPI_EC_MOSIAP_SPI_EC_MISOSCP_JTAG0_TMSSCP_JTAG0_TCKSCP_JTAG0_TDOSCP_JTAG0_TDIAP_SPI_FLASH_CS_LAP_SPI_FLASH_CLKAP_SPI_FLASH_MOSIAP_SPI_FLASH_MISOcr50-irq-default-pinsMpins-gsc-ap-int-odl�X�cros-ec-irq-default-pins0pins-ec-ap-int-odl��e�i2c0-default-pinsGpins-bus� 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compatibleinterrupt-parent#address-cells#size-cellsmodelgce0gce1i2c0i2c1i2c2i2c3i2c4i2c5i2c7mmc0mmc1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptscpusnum-channelswakeup-delay-msmediatek,platformstatus#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesmediatek,rsel-resistance-in-si-unitpinctrl-namespinctrl-0gpio-line-namespinmuxinput-enablebias-pull-upbias-disabledrive-strength-microampdrive-strengthbias-pull-downoutput-highoutput-low#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extendedregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#iommu-cells#mbox-cellsfirmware-namememory-regionmediatek,rpmsg-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-names#io-channel-cellsmediatek,pad-selectspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapphysmediatek,syscon-wakeupwakeup-sourcevusb33-supplyvbus-supplybus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablepinctrl-1vmmc-supplyvqmmc-supplycap-sd-highspeedcd-gpiosno-mmcsd-uhs-sdr50sd-uhs-sdr104usb2-lpm-disablespi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsinterrupt-namesi2c-scl-internal-delay-nsvcc-supplyhid-descr-addrpost-power-on-delay-msvdd-supplynvmem-cellsnvmem-cell-namesmediatek,smimediatek,larb-idmediatek,larbsiommusmediatek,gce-client-regmediatek,gce-eventsstdout-pathregulator-boot-onvin-supplyenable-active-highno-map