p8 ( '&8Qualcomm Technologies, Inc. SDX65 MTP>qcom,sdx65-mtpqcom,sdx65ImemoryWmemorycclocksxo-board >fixed-clockg wxo_boardsleep-clk >fixed-clockg wsleep_clkcpuscpu@0Wcpu>arm,cortex-a7cpscipsci >arm,psci-1.0smcreserved-memoryreserved-memory@8fee0000 >qcom,cmd-dbcsoc >simple-busclock-controller@100000>qcom,gcc-sdx65ctbi_tcxobi_tcxo_aosleep_clkserial@831000%>qcom,msm-uartdm-v1.4qcom,msm-uartdmc  coreifaceokpinctrl@f100000>qcom,sdx65-tlmmc0  m'*interrupt-controller@b210000>qcom,sdx65-pdcqcom,pdcc !;44 *'interrupt-controller@17800000>qcom,msm-qgic2'*c timer@17820000>arm,armv7-timer-memcg$frame@17821000Kc frame@17823000K c0 disabledframe@17824000K c@ disabledframe@17825000K cP disabledframe@17826000K c` disabledframe@17827000K cp disabledframe@17828000K c disabledframe@17829000K c disabledrsc@17830000 Xapps_rsc>qcom,rpmh-rscc ^drv-0drv-1h x clock-controller>qcom,sdx65-rpmh-clkxotimer>arm,armv7-timer0    g$aliases/soc/serial@831000chosenserial0:115200n8 #address-cells#size-cellsqcom,msm-idinterrupt-parentmodelcompatibleqcom,board-iddevice_typeregclock-frequencyclock-output-names#clock-cellsphandleenable-methodrangesno-mapclocksclock-names#reset-cellsinterruptsstatusgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellsqcom,pdc-rangesframe-numberlabelreg-namesqcom,tcs-offsetqcom,drv-idqcom,tcs-configserial0stdout-path