g8( dTgumstix,omap3-overo-chestnut43gumstix,omap3-overoti,omap3630ti,omap36xxti,omap3 +37OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000 {/displaycpus+cpu@0arm,cortex-a8cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus +  pinmux@30 ti,omap3-padconfpinctrl-single08+'<Zwdefaultpinmux_uart2_pins <>@Bpinmux_i2c1_pinspinmux_mmc1_pins0pinmux_mmc2_pins0(*,.02pinmux_w3cbw003c_pinslpinmux_hsusb2_pins@      pinmux_twl4030_pinsApinmux_i2c3_pinspinmux_uart3_pinsnppinmux_dss_dpi_pins pinmux_lte430_pinsD pinmux_backlight_pinsF#pinmux_mcspi1_pins pinmux_ads7846_pins scm_conf@270sysconsimple-busp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+mcbsp5_mux_fck@68ti,composite-mux-clockh mcbsp5_fckti,composite-clock mcbsp1_mux_fck@4ti,composite-mux-clock mcbsp1_fckti,composite-clock mcbsp2_mux_fck@4ti,composite-mux-clock mcbsp2_fckti,composite-clockmcbsp3_mux_fck@68ti,composite-mux-clock hmcbsp3_fckti,composite-clockmcbsp4_mux_fck@68ti,composite-mux-clock hmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+'<Zpinmux_twl4030_vpins target-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `Lrevsyscsyss  (ick+ H ` aes1@0 ti,omap3-aesP5  :txrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLrevsyscsyss  (ick+ H P aes2@0 ti,omap3-aesP5AB:txrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockDYosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clockTp_"sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clockvdpll3_m2x2_ckfixed-factor-clockv!dpll4_x2_ckfixed-factor-clock vcorex2_fckfixed-factor-clock!v#wkup_l4_ickfixed-factor-clock"vRcorex2_d3_fckfixed-factor-clock#vcorex2_d5_fckfixed-factor-clock#vclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockDomap_32k_fck fixed-clockDDvirt_12m_ck fixed-clockDvirt_13m_ck fixed-clockD]@virt_19200000_ck fixed-clockD$virt_26000000_ck fixed-clockDvirt_38_4m_ck fixed-clockDIdpll4_ck@d00ti,omap3-dpll-per-j-type-clock"" D 0 dpll4_m2_ck@d48ti,divider-clock T? H_$dpll4_m2x2_mul_ckfixed-factor-clock$v%dpll4_m2x2_ck@d00ti,hsdiv-gate-clock% &omap_96m_alwon_fckfixed-factor-clock&v-dpll3_ck@d00ti,omap3-dpll-core-clock"" @ 0dpll3_m3_ck@1140ti,divider-clockT@_'dpll3_m3x2_mul_ckfixed-factor-clock'v(dpll3_m3x2_ck@d00ti,hsdiv-gate-clock(  )emu_core_alwon_ckfixed-factor-clock)vfsys_altclk fixed-clockD2mcbsp_clks fixed-clockDdpll3_m2_ck@d40ti,divider-clockT @_core_ckfixed-factor-clockv*dpll1_fck@940ti,divider-clock*T @_+dpll1_ck@904ti,omap3-dpll-clock"+  $ @ 4dpll1_x2_ckfixed-factor-clockv,dpll1_x2m2_ck@944ti,divider-clock,T D_@cm_96m_fckfixed-factor-clock-v.omap_96m_fck@d40 ti,mux-clock." @Idpll4_m3_ck@e40ti,divider-clock T @_/dpll4_m3x2_mul_ckfixed-factor-clock/v0dpll4_m3x2_ck@d00ti,hsdiv-gate-clock0 1omap_54m_fck@d40 ti,mux-clock12 @<cm_96m_d2_fckfixed-factor-clock.v3omap_48m_fck@d40 ti,mux-clock32 @4omap_12m_fckfixed-factor-clock4vKdpll4_m4_ck@e40ti,divider-clock T@_5dpll4_m4x2_mul_ckti,fixed-factor-clock56dpll4_m4x2_ck@d00ti,gate-clock6 dpll4_m5_ck@f40ti,divider-clock T?@_7dpll4_m5x2_mul_ckti,fixed-factor-clock78dpll4_m5x2_ck@d00ti,hsdiv-gate-clock8 ndpll4_m6_ck@1140ti,divider-clock T?@_9dpll4_m6x2_mul_ckfixed-factor-clock9v:dpll4_m6x2_ck@d00ti,hsdiv-gate-clock: ;emu_per_alwon_ckfixed-factor-clock;vgclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock* p=clkout2_src_mux_ck@d70ti,composite-mux-clock*".< p>clkout2_src_ckti,composite-clock=>?sys_clkout2@d70ti,divider-clock?T@ pmpu_ckfixed-factor-clock@vAarm_fck@924ti,divider-clockA $Temu_mpu_alwon_ckfixed-factor-clockAvhl3_ick@a40ti,divider-clock*T @_Bl4_ick@a40ti,divider-clockBT @_Crm_ick@c40ti,divider-clockCT @_gpt10_gate_fck@a00ti,composite-gate-clock"  Egpt10_mux_fck@a40ti,composite-mux-clockD" @Fgpt10_fckti,composite-clockEFgpt11_gate_fck@a00ti,composite-gate-clock"  Ggpt11_mux_fck@a40ti,composite-mux-clockD" @Hgpt11_fckti,composite-clockGHcore_96m_fckfixed-factor-clockIvmmchs2_fck@a00ti,wait-gate-clock mmchs1_fck@a00ti,wait-gate-clock i2c3_fck@a00ti,wait-gate-clock i2c2_fck@a00ti,wait-gate-clock i2c1_fck@a00ti,wait-gate-clock mcbsp5_gate_fck@a00ti,composite-gate-clock   mcbsp1_gate_fck@a00ti,composite-gate-clock   core_48m_fckfixed-factor-clock4vJmcspi4_fck@a00ti,wait-gate-clockJ mcspi3_fck@a00ti,wait-gate-clockJ mcspi2_fck@a00ti,wait-gate-clockJ mcspi1_fck@a00ti,wait-gate-clockJ uart2_fck@a00ti,wait-gate-clockJ uart1_fck@a00ti,wait-gate-clockJ  core_12m_fckfixed-factor-clockKvLhdq_fck@a00ti,wait-gate-clockL core_l3_ickfixed-factor-clockBvMsdrc_ick@a10ti,wait-gate-clockM gpmc_fckfixed-factor-clockMvcore_l4_ickfixed-factor-clockCvNmmchs2_ick@a10ti,omap3-interface-clockN mmchs1_ick@a10ti,omap3-interface-clockN hdq_ick@a10ti,omap3-interface-clockN mcspi4_ick@a10ti,omap3-interface-clockN mcspi3_ick@a10ti,omap3-interface-clockN mcspi2_ick@a10ti,omap3-interface-clockN mcspi1_ick@a10ti,omap3-interface-clockN i2c3_ick@a10ti,omap3-interface-clockN i2c2_ick@a10ti,omap3-interface-clockN i2c1_ick@a10ti,omap3-interface-clockN uart2_ick@a10ti,omap3-interface-clockN uart1_ick@a10ti,omap3-interface-clockN  gpt11_ick@a10ti,omap3-interface-clockN  gpt10_ick@a10ti,omap3-interface-clockN  mcbsp5_ick@a10ti,omap3-interface-clockN  mcbsp1_ick@a10ti,omap3-interface-clockN  omapctrl_ick@a10ti,omap3-interface-clockN dss_tv_fck@e00ti,gate-clock<dss_96m_fck@e00ti,gate-clockIdss2_alwon_fck@e00ti,gate-clock"dummy_ck fixed-clockDgpt1_gate_fck@c00ti,composite-gate-clock" Ogpt1_mux_fck@c40ti,composite-mux-clockD" @Pgpt1_fckti,composite-clockOPaes2_ick@a10ti,omap3-interface-clockN wkup_32k_fckfixed-factor-clockDvQgpio1_dbck@c00ti,gate-clockQ sha12_ick@a10ti,omap3-interface-clockN wdt2_fck@c00ti,wait-gate-clockQ wdt2_ick@c10ti,omap3-interface-clockR wdt1_ick@c10ti,omap3-interface-clockR gpio1_ick@c10ti,omap3-interface-clockR omap_32ksync_ick@c10ti,omap3-interface-clockR gpt12_ick@c10ti,omap3-interface-clockR gpt1_ick@c10ti,omap3-interface-clockR per_96m_fckfixed-factor-clock-v per_48m_fckfixed-factor-clock4vSuart3_fck@1000ti,wait-gate-clockS gpt2_gate_fck@1000ti,composite-gate-clock"Tgpt2_mux_fck@1040ti,composite-mux-clockD"@Ugpt2_fckti,composite-clockTUgpt3_gate_fck@1000ti,composite-gate-clock"Vgpt3_mux_fck@1040ti,composite-mux-clockD"@Wgpt3_fckti,composite-clockVWgpt4_gate_fck@1000ti,composite-gate-clock"Xgpt4_mux_fck@1040ti,composite-mux-clockD"@Ygpt4_fckti,composite-clockXYgpt5_gate_fck@1000ti,composite-gate-clock"Zgpt5_mux_fck@1040ti,composite-mux-clockD"@[gpt5_fckti,composite-clockZ[gpt6_gate_fck@1000ti,composite-gate-clock"\gpt6_mux_fck@1040ti,composite-mux-clockD"@]gpt6_fckti,composite-clock\]gpt7_gate_fck@1000ti,composite-gate-clock"^gpt7_mux_fck@1040ti,composite-mux-clockD"@_gpt7_fckti,composite-clock^_gpt8_gate_fck@1000ti,composite-gate-clock" `gpt8_mux_fck@1040ti,composite-mux-clockD"@agpt8_fckti,composite-clock`agpt9_gate_fck@1000ti,composite-gate-clock" bgpt9_mux_fck@1040ti,composite-mux-clockD"@cgpt9_fckti,composite-clockbcper_32k_alwon_fckfixed-factor-clockDvdgpio6_dbck@1000ti,gate-clockdgpio5_dbck@1000ti,gate-clockdgpio4_dbck@1000ti,gate-clockdgpio3_dbck@1000ti,gate-clockdgpio2_dbck@1000ti,gate-clockd wdt3_fck@1000ti,wait-gate-clockd per_l4_ickfixed-factor-clockCvegpio6_ick@1010ti,omap3-interface-clockegpio5_ick@1010ti,omap3-interface-clockegpio4_ick@1010ti,omap3-interface-clockegpio3_ick@1010ti,omap3-interface-clockegpio2_ick@1010ti,omap3-interface-clocke wdt3_ick@1010ti,omap3-interface-clocke uart3_ick@1010ti,omap3-interface-clocke uart4_ick@1010ti,omap3-interface-clockegpt9_ick@1010ti,omap3-interface-clocke gpt8_ick@1010ti,omap3-interface-clocke gpt7_ick@1010ti,omap3-interface-clockegpt6_ick@1010ti,omap3-interface-clockegpt5_ick@1010ti,omap3-interface-clockegpt4_ick@1010ti,omap3-interface-clockegpt3_ick@1010ti,omap3-interface-clockegpt2_ick@1010ti,omap3-interface-clockemcbsp2_ick@1010ti,omap3-interface-clockemcbsp3_ick@1010ti,omap3-interface-clockemcbsp4_ick@1010ti,omap3-interface-clockemcbsp2_gate_fck@1000ti,composite-gate-clockmcbsp3_gate_fck@1000ti,composite-gate-clockmcbsp4_gate_fck@1000ti,composite-gate-clockemu_src_mux_ck@1140 ti,mux-clock"fgh@iemu_src_ckti,clkdm-gate-clockijpclk_fck@1140ti,divider-clockjT@_pclkx2_fck@1140ti,divider-clockjT@_atclk_fck@1140ti,divider-clockjT@_traceclk_src_fck@1140 ti,mux-clock"fgh@ktraceclk_fck@1140ti,divider-clockk T@_secure_32k_fck fixed-clockDlgpt12_fckfixed-factor-clocklvwdt1_fckfixed-factor-clocklvsecurity_l4_ick2fixed-factor-clockCvmaes1_ick@a14ti,omap3-interface-clockm rng_ick@a14ti,omap3-interface-clockm sha11_ick@a14ti,omap3-interface-clockm des1_ick@a14ti,omap3-interface-clockm cam_mclk@f00ti,gate-clockncam_ick@f10!ti,omap3-no-wait-interface-clockCcsi2_96m_fck@f00ti,gate-clocksecurity_l3_ickfixed-factor-clockBvopka_ick@a14ti,omap3-interface-clocko icr_ick@a10ti,omap3-interface-clockN des2_ick@a10ti,omap3-interface-clockN mspro_ick@a10ti,omap3-interface-clockN mailboxes_ick@a10ti,omap3-interface-clockN ssi_l4_ickfixed-factor-clockCvvsr1_fck@c00ti,wait-gate-clock" sr2_fck@c00ti,wait-gate-clock" sr_l4_ickfixed-factor-clockCvdpll2_fck@40ti,divider-clock*T@_pdpll2_ck@4ti,omap3-dpll-clock"p$@4qdpll2_m2_ck@44ti,divider-clockqTD_riva2_ck@0ti,wait-gate-clockrmodem_fck@a00ti,omap3-interface-clock" sad2d_ick@a10ti,omap3-interface-clockB mad2d_ick@a18ti,omap3-interface-clockB mspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock# sssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock# @$tssi_ssr_fck_3430es2ti,composite-clockstussi_sst_fck_3430es2fixed-factor-clockuvhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockM ssi_ick_3430es2@a10ti,omap3-ssi-interface-clockv usim_gate_fck@c00ti,composite-gate-clockI  sys_d2_ckfixed-factor-clock"vxomap_96m_d2_fckfixed-factor-clockIvyomap_96m_d4_fckfixed-factor-clockIvzomap_96m_d8_fckfixed-factor-clockIv{omap_96m_d10_fckfixed-factor-clockIv |dpll5_m2_d4_ckfixed-factor-clockwv}dpll5_m2_d8_ckfixed-factor-clockwv~dpll5_m2_d16_ckfixed-factor-clockwvdpll5_m2_d20_ckfixed-factor-clockwvusim_mux_fck@c40ti,composite-mux-clock("xyz{|}~ @_usim_fckti,composite-clockusim_ick@c10ti,omap3-interface-clockR  dpll5_ck@d04ti,omap3-dpll-clock""  $ L 4dpll5_m2_ck@d50ti,divider-clockT P_wsgx_gate_fck@b00ti,composite-gate-clock* core_d3_ckfixed-factor-clock*vcore_d4_ckfixed-factor-clock*vcore_d6_ckfixed-factor-clock*vomap_192m_alwon_fckfixed-factor-clock&vcore_d2_ckfixed-factor-clock*vsgx_mux_fck@b40ti,composite-mux-clock . @sgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clockB cpefuse_fck@a08ti,gate-clock" ts_fck@a08ti,gate-clockD usbtll_fck@a08ti,wait-gate-clockw usbtll_ick@a18ti,omap3-interface-clockN mmchs3_ick@a10ti,omap3-interface-clockN mmchs3_fck@a00ti,wait-gate-clock dss1_alwon_fck_3430es2@e00ti,dss-gate-clockdss_ick_3430es2@e10ti,omap3-dss-interface-clockCusbhost_120m_fck@1400ti,gate-clockwusbhost_48m_fck@1400ti,dss-gate-clock4usbhost_ick@1410ti,omap3-dss-interface-clockCuart4_fck@1000ti,wait-gate-clockSclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainlemu_clkdmti,clockdomainjdpll4_clkdmti,clockdomain wkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainqd2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,syscH2H2 revsyscQfckick+ H2counter@0ti,omap-counter32k interrupt-controller@48200000ti,omap3-intc'H target-module@48056000ti,sysc-omap2ti,syscH`H`,H`(revsyscsyss #  (Mick+ H`dma-controller@0ti,omap3630-sdmati,omap-sdma -8 E`gpio@48310000ti,omap3-gpioH1gpio1Rdt'gpio@49050000ti,omap3-gpioIgpio2dt'gpio@49052000ti,omap3-gpioI gpio3dt'gpio@49054000ti,omap3-gpioI@ gpio4dt'gpio@49056000ti,omap3-gpioI`!gpio5dt'!gpio@49058000ti,omap3-gpioI"gpio6dt' serial@4806a000ti,omap3-uartH H512:txrxuart1Dlserial@4806c000ti,omap3-uartHI534:txrxuart2Dlwdefaultserial@49020000ti,omap3-uartIJn556:txrxuart3Dlwdefaulti2c@48070000 ti,omap3-i2cH8+i2c1wdefaultD'@twl@48H  ti,twl4030'wdefaultaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci  vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpiodt'twl4030-usbti,twl4030-usb   pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad(8madcti,twl4030-madcKi2c@48072000 ti,omap3-i2cH 9+i2c2 ]disabledi2c@48060000 ti,omap3-i2cH=+i2c3wdefaultDeeprom@51 atmel,24c01Qdlis33de@1dst,lis33dest,lis3lv02dmx   ,;JYhxwx&& ]disabledmailbox@48094000ti,omap3-mailboxmailboxH @mbox-dsp  spi@48098000ti,omap2-mcspiH A+mcspi1@5#$%&'()* :tx0rx0tx1rx1tx2rx2tx3rx3wdefaultads7846@0wdefault ti,ads7846!`  3@IR[dtspi@4809a000ti,omap2-mcspiH B+mcspi2 5+,-.:tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3 5:tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi45FG:tx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc15=>:txrxwdefaultmmc@480b4000ti,omap3-hsmmcH @Vmmc25/0:txrxwdefaultmmc@480ad000ti,omap3-hsmmcH ^mmc35MN:txrx ]disabledmmu@480bd400ti,omap2-iommuH mmu_ispmmu@5d000000ti,omap2-iommu]mmu_iva ]disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp15 :txrxfck ]disabledtarget-module@480a0000ti,sysc-omap2ti,syscH <H @H Drevsyscsyss (ick+ H rng@0 ti,omap2-rng 4mcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone5!":txrxfckick]okaymcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetone5:txrxfckick ]disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrxmcbsp45:txrxfck& ]disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrxmcbsp55:txrxfck ]disabledsham@480c3000ti,omap3-shamshamH 0d15E:rxtarget-module@48318000ti,sysc-omap2-timerti,syscH1H1H1revsyscsyss ' (fckick+ H17Ktimer@0ti,omap3430-timerfck%VeuDtarget-module@49032000ti,sysc-omap2-timerti,syscI I I revsyscsyss ' (fckick+ I timer@0ti,omap3430-timer&timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11target-module@48304000ti,sysc-omap2-timerti,syscH0@H0@H0@revsyscsyss ' (fckick+ H0@timer@0ti,omap3430-timer_Vusbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ ehci-phyohci@48064400ti,ohci-omap3HDLehci@48064800 ti,ehci-omapHHMgpmc@6e000000ti,omap3430-gpmcgpmcn5:rxtx+'dt00+,nand@0,0ti,omap2-nandmicron,mt29c4g96maz   ,bch8<M[,m,",(6@RR ( +partition@0 -SPLpartition@80000 -U-Bootpartition@1c0000 -Environment$partition@280000 -Kernel(partition@780000 -Filesystemethernet@gpmcsmsc,lan9221smsc,lan9115 3 >M[*m$   P* ^$<6$ l    *           usb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hs , 7 ?  H W   _usb2-phy  i2dss@48050000 ti,omap3-dssH]okay dss_corefck+wdefault dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll ]disabled dss_dsi1 fcksys_clk+encoder@48050800ti,omap3-rfbiH ]disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  ]disabled dss_vencfcktv_dac_clkportendpoint o "ssi-controller@48058000 ti,omap3-ssissi]okayHHsysgddGgdd_mpu+ u ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFserial@49042000ti,omap3-uartI P5QR:txrxuart4Dlregulator-abb-mpu ti,abb-v1 abb_mpu_iva+H0rH0hbase-addressint-address "  ` sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singleH%\+'<Zwdefaultpinmux_hsusb2_2_pins0PRT V X Z pinmux_w3cbw003c_2_pins@pinmux_led_pinsJL$pinmux_button_pinsN<%isp@480bc000 ti,omap3-ispH H   ports+bandgap@48002524H%$ti,omap36xx-bandgap target-module@480cb000ti,sysc-omap3630-srti,syscsmartreflex_coreH 8sysc  fck+ H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3630-srti,syscsmartreflex_mpu_ivaH 8sysc  fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivatarget-module@50000000ti,sysc-omap4ti,syscPP revsysc  fckick+ Popp-tableoperating-points-v2-ti-cpuopp50-300000000  ssssss  opp100-600000000 #F OOOOOO opp130-800000000 / 777777 opp1g-1000000000 ;  opp_supplyti,omap-opp-supply +thermal-zonescpu-thermal F \ jN  wtripscpu_alert 8 passivecpu_crit _  criticalcooling-mapsmap0  memory@0memoryled-controller pwm-ledsled-1 -overo:blue:COM w5  mmc0soundti,omap-twl4030 overo hsusb2_power_regregulator-fixed hsusb2_vbusLK@LK@ ;  p hsusb2_phyusb-nop-xceiv  regulator-w3cbw003c-npoweronregulator-fixedregulator-w3cbw003c-npoweron2Z2Z ; regulator-w3cbw003c-wifi-nresetwdefaultregulator-fixed regulator-w3cbw003c-wifi-nreset2Z2Z ; 'lis33-3v3-regregulator-fixedlis33-3v3-reg2Z2Zlis33-1v8-regregulator-fixedlis33-1v8-regw@w@displaysamsung,lte430wq-f0cpanel-dpi -lcd43wdefault  !portendpoint o"panel-timingDa + 3 ; H T) ^ j w     ads7846-regregulator-fixed ads7846-reg2Z2Zbacklightgpio-backlightwdefault# ! leds gpio-ledswdefault$heartbeat -overo:red:gpio21  heartbeatgpio22 -overo:blue:gpio22 gpio_keys gpio-keyswdefault%+button0 -button0  button1 -button1  regulator-vddvarioregulator-fixed vddvario regulator-vdd33aregulator-fixedvdd33a  compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3display0device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellsphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxwakeup-sourceti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicepwmsmax-brightnesslinux,default-triggerti,modelti,mcbspstartup-delay-usenable-active-highreset-gpiosenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-onlinux,code