m8g(f)tronsmart,orion-r68-metarockchip,rk3368 +7Rockchip Orion R68aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0c0000/mmc@ff0f0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53psciarm-pmuarm,armv8-pmuv3`pqrstuvw  psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clockn6 xin24m Fmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @- ;  D r vBbiuciuciu-driveciu-sampleN Y `resetlokays}default mmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @-р ;  E s wBbiuciuciu-driveciu-sampleN !Y `reset ldisabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@-р ;  G u yBbiuciuciu-driveciu-sampleN #Y `resetlokays default saradc@ff100000rockchip,saradc $; I [Bsaradcapb_pclkY W `saradc-apblokay,spi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi; A RBspiclkapb_pclk ,default+ ldisabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi; B SBspiclkapb_pclk -default+ ldisabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi; C TBspiclkapb_pclk )default !+ ldisabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+Bi2c; Ndefault" ldisabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+Bi2c; Odefault# ldisabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+Bi2c; Pdefault$ ldisabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+Bi2c; Qdefault% ldisabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartn6; M UBbaudclkapb_pclk 78B ldisabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartn6; N VBbaudclkapb_pclk 88B ldisabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartn6; P XBbaudclkapb_pclk :8B ldisabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartn6; Q YBbaudclkapb_pclk ;8Blokaydefault&dma-controller@ff250000arm,pl330arm,primecell%@OZu;  Bapb_pclkthermal-zonescpu-thermald'tripscpu_alert0$passive(cpu_alert18passive)cpu_crits criticalcooling-mapsmap0(0map1)0 gpu-thermald'tripsgpu_alert08passive*gpu_crit8 criticalcooling-mapsmap0*0tsadc@ff280000rockchip,rk3368-tsadc( %; H ZBtsadcapb_pclkY  `tsadc-apbinitdefaultsleep+,+s ldisabled'ethernet@ff290000rockchip,rk3368-gmac) ,macirq<-8;  f g c ]MBstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_maclokayI Y.pinput}/rgmiidefault0 1  'B@0usb@ff500000 generic-ehciP ; lokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X ; Botgotg@@ lokaydma-controller@ff600000arm,pl330arm,primecell`@OZu;  Bapb_pclkGi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ce; LBi2c <default2+lokaysyr827@40silergy,syr827@3vdd_cpuB,^ 4v`@3rtc@51haoyu,hym8563Q  xin32ki2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+Bi2c; Mdefault4 ldisabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault5; _ ldisabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault6; _ ldisabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh ; _ ldisabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default7; _ ldisabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uarti; O WBbaudclkapb_pclk 9default88Blokaymbox@ff6b0000rockchip,rk3368-mailboxk0; E Bpclk_mailbox ldisabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdspower-controller!rockchip,rk3368-power-controller+Jpower-domain@12 ;       c h g n o r s f d d h i l k j n m$9:;<=>?@Apower-domain@14 ;  o p BCDpower-domain@16; @Esyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdsKio-domains&rockchip,rk3368-pmu-io-voltage-domain ldisabledreboot-modesyscon-reboot-mode RBRB'RB 7RBclock-controller@ff760000rockchip,rk3368-cruv;FBxin24m<- C syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw-io-domains"rockchip,rk3368-io-voltage-domain ldisabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt; p Olokaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  B; a U Bpclktimerspdif@ff880000rockchip,rk3368-spdif 6; S  BmclkhclkPGUtxdefaultH_ ldisabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (Bi2s_clki2s_hclk; T PGGUtxrx_ ldisabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5Bi2s_clki2s_hclk; R PGGUtxrxdefaultI_ ldisablediommu@ff900800rockchip,iommu ;  BaclkifacepJ ~ ldisablediommu@ff914000rockchip,iommu @P ;  Baclkiface~pJ  ldisablediommu@ff930300rockchip,iommu ;  BaclkifacepJ ~ ldisablediommu@ff9a0440rockchip,iommu @@@ ;  Baclkiface~ ldisablediommu@ff9a0800rockchip,iommu  ;  Baclkiface~ ldisabledqos@ffad0000rockchip,rk3368-qossyscon 9qos@ffad0080rockchip,rk3368-qossyscon :qos@ffad0100rockchip,rk3368-qossyscon ;qos@ffad0180rockchip,rk3368-qossyscon <qos@ffad0200rockchip,rk3368-qossyscon =qos@ffad0280rockchip,rk3368-qossyscon >qos@ffad0300rockchip,rk3368-qossyscon ?qos@ffad0380rockchip,rk3368-qossyscon @qos@ffad0400rockchip,rk3368-qossyscon Aqos@ffae0000rockchip,rk3368-qossyscon Bqos@ffae0100rockchip,rk3368-qossyscon Cqos@ffae0180rockchip,rk3368-qossyscon Dqos@ffaf0000rockchip,rk3368-qossyscon Eefuse@ffb00000rockchip,rk3368-efuse +; q Bpclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400@ @ `   pinctrlrockchip,rk3368-pinctrl<-K+gpio@ff750000rockchip,gpio-banku; @ QUgpio@ff780000rockchip,gpio-bankx; A Rgpio@ff790000rockchip,gpio-banky; B SSgpio@ff7a0000rockchip,gpio-bankz; C T1pcfg-pull-upNpcfg-pull-down Qpcfg-pull-noneOpcfg-pull-none-12ma% Pemmcemmc-clk4Lemmc-cmd4Memmc-pwr4Nemmc-bus14Nemmc-bus4@4NNNNemmc-bus84MMMMMMMMemmc-reset4ORgmacrgmii-pins4OOOP P PPP POOOOOO0rmii-pins4OOOP P POOOOi2c0i2c0-xfer 4OO2i2c1i2c1-xfer 4OO4i2c2i2c2-xfer 4 OO"i2c3i2c3-xfer 4OO#i2c4i2c4-xfer 4OO$i2c5i2c5-xfer 4OO%i2si2s-8ch-bus4 O OOOOOOOOIpwm0pwm0-pin4O5pwm1pwm1-pin4O6pwm3pwm3-pin4O7sdio0sdio0-bus14Nsdio0-bus4@4NNNNsdio0-cmd4Nsdio0-clk4Osdio0-cd4Nsdio0-wp4Nsdio0-pwr4Nsdio0-bkpwr4Nsdio0-int4Nsdmmcsdmmc-clk4 L sdmmc-cmd4 M sdmmc-cd4 M sdmmc-bus14Msdmmc-bus4@4MMMMspdifspdif-tx4OHspi0spi0-clk4Nspi0-cs04Nspi0-cs14Nspi0-tx4Nspi0-rx4Nspi1spi1-clk4Nspi1-cs04Nspi1-cs14Nspi1-rx4Nspi1-tx4Nspi2spi2-clk4 Nspi2-cs04 N!spi2-rx4 N spi2-tx4 Ntsadcotp-pin4O+otp-out4O,uart0uart0-xfer 4NOuart0-cts4Ouart0-rts4Ouart1uart1-xfer 4NOuart1-cts4Ouart1-rts4Ouart2uart2-xfer 4NO8uart3uart3-xfer 4NOuart3-cts4Ouart3-rts4Ouart4uart4-xfer 4NO&uart4-cts4Ouart4-rts4Opcfg-pull-none-drv-8ma%Lpcfg-pull-up-drv-8ma%Mkeyspwr-key4QTledsstby-pwren4 OWled-ctl4OVusbhost-vbus-drv4OXchosenBserial2:115200n8memorymemoryemmc-pwrseqmmc-pwrseq-emmcRdefault NSexternal-gmac-clock fixed-clock sY@  ext_gmac.gpio-keys gpio-keysdefaultTkey-powerZ TU hGPIO Powerntgpio-leds gpio-ledsled-0 T1horion:red:leddefaultVyonled-1 TU horion:blue:leddefaultWyoffvcc18-regulatorregulator-fixed3vcc_18^w@vw@3vcc-host-regulatorregulator-fixed UdefaultX 3vcc_host3vcc-io-regulatorregulator-fixed3vcc_io^2Zv2Z3Yvcc-lan-regulatorregulator-fixed3vcc_lan^2Zv2ZY/vcc-sd-regulatorregulator-fixed3vcc_sd 1 ^w@v2ZYvcc-sys-regulatorregulator-fixed3vcc_sys^LK@vLK@3vcc-io-sd-regulatorregulator-fixed 3vccio_sd^w@v2ZYvccio-wl-regulatorregulator-fixed 3vccio_wl^2Zv2ZYvdd-10-regulatorregulator-fixed3vdd_10^B@vB@3 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusbus-widthcap-sd-highspeedcard-detect-delaypinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-pwrseqmmc-hs200-1_2vmmc-hs200-1_8vnon-removable#io-channel-cellsvref-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#sound-dai-cellspower-domains#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codedefault-state